Cover Image

Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Suzuki, Yasunari, Sugiyama, Takanori, Arai, Tomochika, Liao, Wang, Inoue, Koji, Tanimoto, Teruo
Format:	Preprint
Published:	2024
Subjects:	Quantum Physics Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing
by: Kobori, Takumi, et al.
Published: (2024)

High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture
by: Ueno, Yosuke, et al.
Published: (2024)

SFQ counter-based precomputation for large-scale cryogenic VQE machines
by: Ueno, Yosuke, et al.
Published: (2024)

C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms
by: Ueno, Yosuke, et al.
Published: (2024)

bitSMM: A bit-Serial Matrix Multiplication Accelerator
by: Antunes, Pedro, et al.
Published: (2026)

ABI: A tightly integrated, unified, sparsity-aware, reconfigurable, compute near-register file/cache GPU architecture with light-weight softmax for deep learning, linear algebra, and Ising compute
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs
by: Kida, Misaki, et al.
Published: (2025)

The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates
by: Ilmberger, Joscha, et al.
Published: (2025)

Design high-confidence computers using trusted instructional set architecture and emulators
by: Wang, Shuangbao Paul
Published: (2025)

AxLLM: accelerator architecture for large language models with computation reuse capability
by: Ahadi, Soroush, et al.
Published: (2025)

Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
by: Geens, Robin, et al.
Published: (2026)

A modular architecture for IMU-based data gloves
by: Carfì, Alessandro, et al.
Published: (2024)

Modulo-$(2^{2n}+1)$ Arithmetic via Two Parallel n-bit Residue Channels
by: Jaberipur, Ghassem, et al.
Published: (2024)

M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization
by: Hu, Weiming, et al.
Published: (2026)

Semicustom Frontend VLSI Design and Analysis of a 32-bit Brent-Kung Adder in Cadence Suite
by: Singh, Yashvardhan
Published: (2025)

M-ANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type
by: Hu, Weiming, et al.
Published: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)

Design of a 6-bit Threshold Inverter Quantization (TIQ) Flash Analog to Digital Converter (ADC)
by: Sarkar, Noyon Kumar, et al.
Published: (2025)

Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
by: Ando, Takuto, et al.
Published: (2025)

Enhancing software-hardware co-design for HEP by low-overhead profiling of single- and multi-threaded programs on diverse architectures with Adaptyst
by: Graczyk, Maksymilian, et al.
Published: (2025)

BitROM: Weight Reload-Free CiROM Architecture Towards Billion-Parameter 1.58-bit LLM Inference
by: Zhang, Wenlun, et al.
Published: (2025)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
by: Reinwardt, Christopher, et al.
Published: (2025)

A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
by: Yang, Junyi, et al.
Published: (2025)

Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
by: Ke, Chih-Hua
Published: (2026)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
by: Sauter, Philippe, et al.
Published: (2025)

Implementation of a 8-bit Wallace Tree Multiplier
by: Biswas, Ayan, et al.
Published: (2025)

GRAMC: General-purpose and reconfigurable analog matrix computing architecture
by: Pan, Lunshuai, et al.
Published: (2025)

The Bicameral Cache: a split cache for vector architectures
by: Rebolledo, Susana, et al.
Published: (2024)

A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

Sustainable operation of research infrastructure for novel computing
by: Stradmann, Yannik, et al.
Published: (2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
by: Scheffler, Paul, et al.
Published: (2025)

PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
by: Yin, Ruokai, et al.
Published: (2025)

On Approximate 8-bit Floating-Point Operations Using Integer Operations
by: Lindberg, Theodor, et al.
Published: (2024)

4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation
by: Kihara, Fuyuki, et al.
Published: (2025)

Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
by: Nayan, Md Mizanur Rahaman, et al.
Published: (2025)

GAVINA: flexible aggressive undervolting for bit-serial mixed-precision DNN acceleration
by: Fornt, Jordi, et al.
Published: (2025)

KANtize: Exploring Low-bit Quantization of Kolmogorov-Arnold Networks for Efficient Inference
by: Errabii, Sohaib, et al.
Published: (2026)

PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs
by: Malekar, Jinendra, et al.
Published: (2025)

A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)