Histogram-Equalized Quantization for logic-gated Residual Neural Networks
Fuente:
arXiv
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| Autori principali: | , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866916558121467904 |
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| author | Nguyen, Van Thien Guicquero, William Sicard, Gilles |
| author_facet | Nguyen, Van Thien Guicquero, William Sicard, Gilles |
| contents | Adjusting the quantization according to the data or to the model loss seems mandatory to enable a high accuracy in the context of quantized neural networks. This work presents Histogram-Equalized Quantization (HEQ), an adaptive framework for linear symmetric quantization. HEQ automatically adapts the quantization thresholds using a unique step size optimization. We empirically show that HEQ achieves state-of-the-art performances on CIFAR-10. Experiments on the STL-10 dataset even show that HEQ enables a proper training of our proposed logic-gated (OR, MUX) residual networks with a higher accuracy at a lower hardware complexity than previous work. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_04517 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Histogram-Equalized Quantization for logic-gated Residual Neural Networks Nguyen, Van Thien Guicquero, William Sicard, Gilles Machine Learning Hardware Architecture Adjusting the quantization according to the data or to the model loss seems mandatory to enable a high accuracy in the context of quantized neural networks. This work presents Histogram-Equalized Quantization (HEQ), an adaptive framework for linear symmetric quantization. HEQ automatically adapts the quantization thresholds using a unique step size optimization. We empirically show that HEQ achieves state-of-the-art performances on CIFAR-10. Experiments on the STL-10 dataset even show that HEQ enables a proper training of our proposed logic-gated (OR, MUX) residual networks with a higher accuracy at a lower hardware complexity than previous work. |
| title | Histogram-Equalized Quantization for logic-gated Residual Neural Networks |
| topic | Machine Learning Hardware Architecture |
| url | https://arxiv.org/abs/2501.04517 |