Towards High-Performance Network Coding: FPGA Acceleration With Bounded-value Generators
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arXiv
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| Hauptverfasser: | , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866915095663083520 |
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| author | Qing, Jiaxin Leong, Philip H. W. Lee, Kin Hong Yeung, Raymond W. |
| author_facet | Qing, Jiaxin Leong, Philip H. W. Lee, Kin Hong Yeung, Raymond W. |
| contents | Network coding enhances performance in network communications and distributed storage by increasing throughput and robustness while reducing latency. Batched Sparse (BATS) codes are a class of capacity-achieving network codes, but their practical applications are hindered by their structure, computational intensity, and power demands of finite field operations. Most literature focuses on algorithmic-level techniques to improve coding efficiency. Optimization with an algorithm/hardware co-designing approach has long been neglected. Leveraging the unique structure of BATS codes, we first present CS-BATS, a hardware-friendly variant. Next we propose a simple but effective bounded-value generator, to reduce the size of a finite field multiplier by up to 70%. Finally, we report on a scalable and resource-efficient FPGA-based network coding accelerator that achieves a throughput of 27 Gbps, a speedup of more than 300 over software. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_05033 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Towards High-Performance Network Coding: FPGA Acceleration With Bounded-value Generators Qing, Jiaxin Leong, Philip H. W. Lee, Kin Hong Yeung, Raymond W. Hardware Architecture Information Theory Network coding enhances performance in network communications and distributed storage by increasing throughput and robustness while reducing latency. Batched Sparse (BATS) codes are a class of capacity-achieving network codes, but their practical applications are hindered by their structure, computational intensity, and power demands of finite field operations. Most literature focuses on algorithmic-level techniques to improve coding efficiency. Optimization with an algorithm/hardware co-designing approach has long been neglected. Leveraging the unique structure of BATS codes, we first present CS-BATS, a hardware-friendly variant. Next we propose a simple but effective bounded-value generator, to reduce the size of a finite field multiplier by up to 70%. Finally, we report on a scalable and resource-efficient FPGA-based network coding accelerator that achieves a throughput of 27 Gbps, a speedup of more than 300 over software. |
| title | Towards High-Performance Network Coding: FPGA Acceleration With Bounded-value Generators |
| topic | Hardware Architecture Information Theory |
| url | https://arxiv.org/abs/2501.05033 |