TransPlace: Transferable Circuit Global Placement via Graph Neural Network
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866912294391250944 |
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| author | Hou, Yunbo Ye, Haoran Yang, Shuwen Zhang, Yingxue Xu, Siyuan Song, Guojie |
| author_facet | Hou, Yunbo Ye, Haoran Yang, Shuwen Zhang, Yingxue Xu, Siyuan Song, Guojie |
| contents | Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_05667 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | TransPlace: Transferable Circuit Global Placement via Graph Neural Network Hou, Yunbo Ye, Haoran Yang, Shuwen Zhang, Yingxue Xu, Siyuan Song, Guojie Machine Learning Artificial Intelligence Hardware Architecture Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%. |
| title | TransPlace: Transferable Circuit Global Placement via Graph Neural Network |
| topic | Machine Learning Artificial Intelligence Hardware Architecture |
| url | https://arxiv.org/abs/2501.05667 |