Cover Image

Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Waqar, Faaiq, Zhang, Jiahao, Lu, Anni, He, Zifan, Cong, Jason, Yu, Shimeng
Format:	Preprint
Published:	2025
Subjects:	Emerging Technologies B.3.1; B.7.1
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache
by: Waqar, Faaiq, et al.
Published: (2025)

CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms
by: Waqar, Faaiq, et al.
Published: (2025)

Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories
by: Lee, Ming-Yen, et al.
Published: (2025)

GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition
by: Li, Peijing, et al.
Published: (2025)

Time Domain Near Memory Computing Engine
by: Antal, Sarthak, et al.
Published: (2026)

ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
by: Tashdid, Ishraq, et al.
Published: (2025)

Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation
by: Abouagour, Faris
Published: (2026)

A Comparative Study of Digital Memristor-Based Processing-In-Memory from a Device and Reliability Perspective
by: Neuner, Thomas, et al.
Published: (2026)

Microelectronic Morphogenesis: Progress towards Artificial Organisms
by: McCaskill, John S., et al.
Published: (2023)

TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
by: Guan, Hongyi, et al.
Published: (2026)

Fabrication and Experimental Study of Prototype NdFeB Helical Undulators
by: Balal, Nezah, et al.
Published: (2025)

Magnetic flux imaging in a 3D superconductor integrated circuit
by: Ren, Tong, et al.
Published: (2025)

A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process
by: Reddy, Harshith, et al.
Published: (2025)

L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering
by: Han, Yuntao, et al.
Published: (2025)

L-Sort: An Efficient Hardware for Real-time Multi-channel Spike Sorting with Localization
by: Han, Yuntao, et al.
Published: (2024)

NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
by: Fu, Siqing, et al.
Published: (2025)

A WASM-Subset Stack Architecture for Low-cost FPGAs using Open-Source EDA Flows
by: Chakrabarti, Aradhya
Published: (2025)

3SAT on an All-to-All-Connected CMOS Ising Solver Chip
by: Cılasun, Hüsrev, et al.
Published: (2023)

AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems
by: Tashdid, Ishraq, et al.
Published: (2025)

Spiking Neural Networks for SAR Interferometric Phase Unwrapping: A Theoretical Framework for Energy-Efficient Processing
by: Bara, Marc
Published: (2025)

RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines
by: Ojika, Dave, et al.
Published: (2025)

A 65 nm Bayesian Neural Network Accelerator with 360 fJ/Sample In-Word GRNG for AI Uncertainty Estimation
by: Enciso, Zephan M., et al.
Published: (2025)

Toward an Ion-Based Large-Scale Integrated Circuit: Circuit Level Design, Simulation, and Integration of Iontronic Components
by: Fraiman, Noa Edri, et al.
Published: (2024)

Dataflow & Tiling Strategies in Edge-AI FPGA Accelerators: A Comprehensive Literature Review
by: Li, Richie
Published: (2025)

DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
by: Zhang, Yuhan, et al.
Published: (2026)

basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
by: Kang, Hyun Woo, et al.
Published: (2025)

Spectral engineering of optical microresonators in anisotropic lithium niobate crystal
by: Zhang, Ke, et al.
Published: (2024)

RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
by: Kang, Hyunwoo
Published: (2026)

Biological Intuition on Digital Hardware: An RTL Implementation of Poisson-Encoded SNNs for Static Image Classification
by: Das, Debabrata, et al.
Published: (2026)

Attractor-Keyed Memory
by: Berloff, Natalia G.
Published: (2026)

Effective tuning methods for few-electron regime in gate-defined quantum dots
by: Yang, Chanuk, et al.
Published: (2024)

Toward Thermodynamic Reservoir Computing: Exploring SHA-256 ASICs as Potential Physical Substrates
by: de Lafuente, Francisco Angulo, et al.
Published: (2026)

Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer
by: Li, Richie, et al.
Published: (2025)

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
by: Aspros, Maxime Henri, et al.
Published: (2025)

A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults
by: Wei, Shaoqi, et al.
Published: (2025)

Delta6: A Low-Cost, 6-DOF Force-Sensing Flexible End-Effector
by: Feng, Yue, et al.
Published: (2026)

Minimal Neuron Circuits -- Part I: Resonators
by: Nabil, Amr, et al.
Published: (2025)

Minimal Neuron Circuits: Bursters
by: Nabil, Amr, et al.
Published: (2025)

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
by: Yildirim, Muhammed, et al.
Published: (2025)

Lifespan estimate for the semilinear regular Euler-Poisson-Darboux-Tricomi equation
by: Li, Yuequn, et al.
Published: (2025)