Image de couverture de livre

Leveraging ASIC AI Chips for Homomorphic Encryption

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Tong, Jianming, Huang, Tianhao, Dang, Jingtian, de Castro, Leo, Itagi, Anirudh, Golder, Anupam, Ali, Asra, Kun, Jeremy, Jiang, Jevin, Arvind, Suh, G. Edward, Krishna, Tushar
Format:	Preprint
Publié:	2025
Sujets:	Cryptography and Security Hardware Architecture Computation and Language Programming Languages
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

Enabling AI ASICs for Zero Knowledge Proof
par: Tong, Jianming, et autres
Publié: (2026)

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
par: Tong, Jianming, et autres
Publié: (2024)

MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator
par: Tong, Jianming, et autres
Publié: (2026)

Accurate Low-Degree Polynomial Approximation of Non-polynomial Operators for Fast Private Inference in Homomorphic Encryption
par: Tong, Jianming, et autres
Publié: (2024)

SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs
par: Dang, Jingtian, et autres
Publié: (2026)

Digital ASIC Design with Ongoing LLMs: Strategies and Prospects
par: Xiang, Maoyang, et autres
Publié: (2024)

From English to ASIC: Hardware Implementation with Large Language Model
par: Goh, Emil, et autres
Publié: (2024)

AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations
par: Seo, Jamin, et autres
Publié: (2025)

ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
par: Allam, Ahmed, et autres
Publié: (2025)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
par: Chang, Kaiyan, et autres
Publié: (2024)

ChipGPT: How far are we from natural language hardware design
par: Chang, Kaiyan, et autres
Publié: (2023)

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
par: Chen, Zhirong, et autres
Publié: (2025)

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
par: Raj, Ritik, et autres
Publié: (2025)

CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
par: Chang, Che-Ming, et autres
Publié: (2026)

A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation
par: Lei, Jie, et autres
Publié: (2025)

Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
par: Meech, James T.
Publié: (2023)

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
par: Vijayaraghavan, Prashanth, et autres
Publié: (2025)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
par: Niu, Juxin, et autres
Publié: (2025)

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
par: Xu, Siyi, et autres
Publié: (2025)

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
par: Collini, Luca, et autres
Publié: (2026)

The Program Hypergraph: Multi-Way Relational Structure for Geometric Algebra, Spatial Compute, and Physics-Aware Compilation
par: Haynes, Houston
Publié: (2026)

Register Aggregation for Hardware Decompilation
par: Rao, Varun, et autres
Publié: (2024)

VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation
par: Zhao, Yuqin, et autres
Publié: (2025)

HaLoRA: Hardware-aware Low-Rank Adaptation for Large Language Models Based on Hybrid Compute-in-Memory Architecture
par: Wu, Taiqiang, et autres
Publié: (2025)

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
par: Liu, Mingjie, et autres
Publié: (2024)

Relaxed exception semantics for Arm-A (extended version)
par: Simner, Ben, et autres
Publié: (2024)

Aligning Netlist to Source Code using SynAlign
par: Garg, Sakshi, et autres
Publié: (2025)

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
par: Zhao, Zhuorui, et autres
Publié: (2025)

An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
par: Zhang, Weichuang, et autres
Publié: (2024)

WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissions
par: Lin, Zhengyao, et autres
Publié: (2023)

There and Back Again: A Netlist's Tale with Much Egraphin'
par: Smith, Gus Henry, et autres
Publié: (2024)

Scaling Program Synthesis Based Technology Mapping with Equality Saturation
par: Smith, Gus Henry, et autres
Publié: (2024)

SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
par: Chang, Fu-Chieh, et autres
Publié: (2026)

SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
par: Zhuang, Jinming, et autres
Publié: (2024)

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
par: Abdelatty, Manar, et autres
Publié: (2024)

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
par: Chen, Chen, et autres
Publié: (2024)

Tywaves: A Typed Waveform Viewer for Chisel
par: Meloni, Raffaele, et autres
Publié: (2024)

ORAssistant: A Custom RAG-based Conversational Assistant for OpenROAD
par: Kaintura, Aviral, et autres
Publié: (2024)

Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques
par: Lin, Qun-Kai, et autres
Publié: (2025)

HEC: Equivalence Verification Checking for Code Transformation via Equality Saturation
par: Yin, Jiaqi, et autres
Publié: (2025)