Learnable Sparsification of Die-to-Die Communication via Spike-Based Encoding

Fuente: arXiv
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Autores principales: Nardone, Joshua, Zhu, Ruijie, Callenes, Joseph, Elbtity, Mohammed E., Zand, Ramtin, Eshraghian, Jason
Formato: Preprint
Publicado: 2025
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Acceso en línea:
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author Nardone, Joshua
Zhu, Ruijie
Callenes, Joseph
Elbtity, Mohammed E.
Zand, Ramtin
Eshraghian, Jason
author_facet Nardone, Joshua
Zhu, Ruijie
Callenes, Joseph
Elbtity, Mohammed E.
Zand, Ramtin
Eshraghian, Jason
contents Efficient communication is central to both biological and artificial intelligence (AI) systems. In biological brains, the challenge of long-range communication across regions is addressed through sparse, spike-based signaling, minimizing energy and latency. Conversely, modern AI workloads are increasingly constrained by bandwidth, leading to bottlenecks that hamper scalability and efficiency. Inspired by the brain's ability to execute dynamic and complex local computations coupled with sparse inter-neuron communication, we propose heterogeneous neural networks that combine spiking neural networks (SNNs) and artificial neural networks (ANNs) at bandwidth-limited regions, such as chip boundaries, where spike-based communication reduces data transfer overhead. Within each chip, dense ANN computations maintain high throughput, accuracy, and robustness. While SNNs have struggled to algorithmically scale, our approach surmounts this long-standing challenge through algorithm-architecture co-design where learnable sparsity is employed for die-to-die communication by confining spiking layers to specific partitions. This composable design combines high ANN performance with low-bandwidth SNN efficiency. Evaluations on language processing and computer vision exhibit up to 5.3x energy efficiency gains and 15.2x latency reductions, surpassing both purely spiking and non-spiking models. As model size grows, improvements scale accordingly. By targeting the inter-chip communication bottleneck with biologically inspired methods, this approach presents a promising path to more efficient AI systems.
format Preprint
id arxiv_https___arxiv_org_abs_2501_08645
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle Learnable Sparsification of Die-to-Die Communication via Spike-Based Encoding
Nardone, Joshua
Zhu, Ruijie
Callenes, Joseph
Elbtity, Mohammed E.
Zand, Ramtin
Eshraghian, Jason
Hardware Architecture
Efficient communication is central to both biological and artificial intelligence (AI) systems. In biological brains, the challenge of long-range communication across regions is addressed through sparse, spike-based signaling, minimizing energy and latency. Conversely, modern AI workloads are increasingly constrained by bandwidth, leading to bottlenecks that hamper scalability and efficiency. Inspired by the brain's ability to execute dynamic and complex local computations coupled with sparse inter-neuron communication, we propose heterogeneous neural networks that combine spiking neural networks (SNNs) and artificial neural networks (ANNs) at bandwidth-limited regions, such as chip boundaries, where spike-based communication reduces data transfer overhead. Within each chip, dense ANN computations maintain high throughput, accuracy, and robustness. While SNNs have struggled to algorithmically scale, our approach surmounts this long-standing challenge through algorithm-architecture co-design where learnable sparsity is employed for die-to-die communication by confining spiking layers to specific partitions. This composable design combines high ANN performance with low-bandwidth SNN efficiency. Evaluations on language processing and computer vision exhibit up to 5.3x energy efficiency gains and 15.2x latency reductions, surpassing both purely spiking and non-spiking models. As model size grows, improvements scale accordingly. By targeting the inter-chip communication bottleneck with biologically inspired methods, this approach presents a promising path to more efficient AI systems.
title Learnable Sparsification of Die-to-Die Communication via Spike-Based Encoding
topic Hardware Architecture
url https://arxiv.org/abs/2501.08645