Octopus: Enhancing CXL Memory Pods via Sparse Topology
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866908933868748800 |
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| author | Zhong, Yuhong Kazhamiaka, Fiodar Zardoshti, Pantea Teng, Shuwei Fonseca, Rodrigo Hill, Mark D. Berger, Daniel S. |
| author_facet | Zhong, Yuhong Kazhamiaka, Fiodar Zardoshti, Pantea Teng, Shuwei Fonseca, Rodrigo Hill, Mark D. Berger, Daniel S. |
| contents | The Compute Express Link (CXL) interconnect enables compute "pods" that pool memory across servers to reduce cost and improve efficiency. These pods also facilitate pairwise communication whose needs conflict with pooling. Importantly, existing pod designs are small or require indirection through expensive switches. These conventional designs implicitly assume that pods must fully connect all servers to all CXL pooling devices.
This paper breaks with this conventional wisdom by introducing Octopus pods. Octopus directly connects servers to low-port-count CXL pooling devices (e.g., 4 ports) yet scales to large pods without switches by constructing a sparse CXL topology in which each pooling device connects to a carefully chosen subset of servers. Octopus explicitly balances "overlap", where two servers connect to the same pooling device: overlap reduces pooling efficiency but enables low-latency communication. Octopus resolves this tension by grouping servers into "islands" with low-latency intra-island communication and interconnecting islands to favor pooling. We build a three-server CXL pod prototype and simulate scaled pods with 96 servers under measured device characteristics and physical constraints (1.5 m copper cables). On hardware, Octopus RPCs are 3.2x faster than in-rack RDMA and 2.4x faster than CXL switches. In simulation, Octopus achieves net server cost savings of 3-5.4% whereas CXL switches result in a net cost increase. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_09020 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Octopus: Enhancing CXL Memory Pods via Sparse Topology Zhong, Yuhong Kazhamiaka, Fiodar Zardoshti, Pantea Teng, Shuwei Fonseca, Rodrigo Hill, Mark D. Berger, Daniel S. Hardware Architecture The Compute Express Link (CXL) interconnect enables compute "pods" that pool memory across servers to reduce cost and improve efficiency. These pods also facilitate pairwise communication whose needs conflict with pooling. Importantly, existing pod designs are small or require indirection through expensive switches. These conventional designs implicitly assume that pods must fully connect all servers to all CXL pooling devices. This paper breaks with this conventional wisdom by introducing Octopus pods. Octopus directly connects servers to low-port-count CXL pooling devices (e.g., 4 ports) yet scales to large pods without switches by constructing a sparse CXL topology in which each pooling device connects to a carefully chosen subset of servers. Octopus explicitly balances "overlap", where two servers connect to the same pooling device: overlap reduces pooling efficiency but enables low-latency communication. Octopus resolves this tension by grouping servers into "islands" with low-latency intra-island communication and interconnecting islands to favor pooling. We build a three-server CXL pod prototype and simulate scaled pods with 96 servers under measured device characteristics and physical constraints (1.5 m copper cables). On hardware, Octopus RPCs are 3.2x faster than in-rack RDMA and 2.4x faster than CXL switches. In simulation, Octopus achieves net server cost savings of 3-5.4% whereas CXL switches result in a net cost increase. |
| title | Octopus: Enhancing CXL Memory Pods via Sparse Topology |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2501.09020 |