Imagen de Portada

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Benz, Thomas, Ottaviano, Alessandro, Liang, Chaoqun, Balas, Robert, Garofalo, Angelo, Restuccia, Francesco, Biondi, Alessandro, Rossi, Davide, Benini, Luca
Formato:	Preprint
Publicado:	2025
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring
por: Liang, Chaoqun, et al.
Publicado: (2025)

A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
por: Liang, Chaoqun, et al.
Publicado: (2024)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
por: Reinwardt, Christopher, et al.
Publicado: (2025)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
por: Rogenmoser, Michael, et al.
Publicado: (2024)

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
por: Zelioli, Enrico, et al.
Publicado: (2024)

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
por: Ottaviano, Alessandro, et al.
Publicado: (2023)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
por: Garofalo, Angelo, et al.
Publicado: (2025)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
por: Ottaviano, Alessandro, et al.
Publicado: (2024)

TOP: Towards Open & Predictable Heterogeneous SoCs
por: Valente, Luca, et al.
Publicado: (2024)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
por: Ottaviano, Alessandro, et al.
Publicado: (2023)

A Multicast-Capable AXI Crossbar for Many-core Machine Learning Accelerators
por: Colagrande, Luca, et al.
Publicado: (2025)

Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience
por: Conti, Francesco, et al.
Publicado: (2024)

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators
por: Isachi, Victor, et al.
Publicado: (2025)

relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
por: Rogenmoser, Michael, et al.
Publicado: (2025)

O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead
por: Cammarata, Danilo, et al.
Publicado: (2026)

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU
por: Belano, Andrea, et al.
Publicado: (2024)

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
por: Riedel, Samuel, et al.
Publicado: (2024)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
por: Valente, Luca, et al.
Publicado: (2022)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
por: Fischer, Tim, et al.
Publicado: (2024)

MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs
por: Russo, Enrico, et al.
Publicado: (2026)

Development of an Energy-Efficient and Real-Time Data Movement Strategy for Next-Generation Heterogeneous Mixed-Criticality Systems
por: Benz, Thomas
Publicado: (2026)

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
por: Rogenmoser, Michael, et al.
Publicado: (2023)

Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
por: Rogenmoser, Michael, et al.
Publicado: (2026)

Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
por: Cai, Maoyuan, et al.
Publicado: (2026)

VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
por: Wipfli, Max, et al.
Publicado: (2026)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
por: Cammarata, Danilo, et al.
Publicado: (2025)

Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores
por: Colagrande, Luca, et al.
Publicado: (2026)

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
por: İslamoğlu, Gamze, et al.
Publicado: (2025)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
por: Perotti, Matteo, et al.
Publicado: (2024)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
por: Benz, Thomas, et al.
Publicado: (2025)

HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
por: Sauter, Philippe, et al.
Publicado: (2026)

Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking
por: Mazzola, Sergio, et al.
Publicado: (2025)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
por: Zhao, Hongwei, et al.
Publicado: (2025)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
por: Colagrande, Luca, et al.
Publicado: (2025)

FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators
por: Zhang, Chi, et al.
Publicado: (2025)

Exploiting Inaccurate Branch History in Side-Channel Attacks
por: Zhu, Yuhui, et al.
Publicado: (2025)

Optimizing Offload Performance in Heterogeneous MPSoCs
por: Colagrande, Luca, et al.
Publicado: (2024)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
por: Sauter, Philippe, et al.
Publicado: (2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
por: Scheffler, Paul, et al.
Publicado: (2024)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
por: Koenig, Cyril, et al.
Publicado: (2025)