AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
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arXiv
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| Main Authors: | Purayil, Navaneeth Kunhi, Perotti, Matteo, Fischer, Tim, Benini, Luca |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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