:: Library Catalog

Saved in:

Bibliographic Details
Main Authors:	Wainstein, Nicolás, Avitay, Eran, Avner, Eugene
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2501.13238
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Enhanced LPDDR4X PHY in 12 nm FinFET
by: Feldmann, Johannes, et al.
Published: (2025)

A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS
by: Mattar, Jeries, et al.
Published: (2025)

Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning
by: Huijbregts, Lucas, et al.
Published: (2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
by: Scheffler, Paul, et al.
Published: (2025)

Ultra-Low-Power Spiking Neurons in 7 nm FinFET Technology: A Comparative Analysis of Leaky Integrate-and-Fire, Morris-Lecar, and Axon-Hillock Architectures
by: Larsh, Logan, et al.
Published: (2025)

T-REX: A 68-567 μs/token, 0.41-3.95 μJ/token Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization in 16nm FinFET
by: Moon, Seunghyun, et al.
Published: (2025)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
by: Paulin, Gianna, et al.
Published: (2024)

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
by: Torrens, Gabriel, et al.
Published: (2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)

Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
by: Gonski, Julia, et al.
Published: (2024)

Fast Generation of Custom Floating-Point Spatial Filters on FPGAs
by: Campos, Nelson, et al.
Published: (2024)

A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
by: Yang, Junyi, et al.
Published: (2025)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
by: Sauter, Philippe, et al.
Published: (2025)

COFFEE: A Carbon-Modeling and Optimization Framework for HZO-based FeFET eNVMs
by: Wu, Hongbang, et al.
Published: (2026)

Efficient CMOS Invertible Logic Using Stochastic Computing
by: Smithson, Sean C., et al.
Published: (2026)

A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
by: Lefebvre, Martin, et al.
Published: (2023)

2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology
by: Kuriakose, Neethu, et al.
Published: (2025)

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
by: Malagon, Daniel, et al.
Published: (2024)

Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
by: Volk, Jennifer, et al.
Published: (2024)

RecFlash: Fast Recommendation System on In-Storage Computing with Frequency-Based Data Mapping
by: Baik, Jangho, et al.
Published: (2026)

A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators
by: Gonul, Yilmaz Ege, et al.
Published: (2025)

An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
by: Alorda, Bartomeu, et al.
Published: (2024)

Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project
by: Agosta, Giovanni, et al.
Published: (2025)

Design and In-training Optimization of Binary Search ADC for Flexible Classifiers
by: Duarte, Paula Carolina Lozano, et al.
Published: (2024)

Fault Tolerant Design of IGZO-based Binary Search ADCs
by: Duarte, Paula Carolina Lozano, et al.
Published: (2026)

Partial Cross-Compilation and Mixed Execution for Accelerating Dynamic Binary Translation
by: Gu, Yuhao, et al.
Published: (2025)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis
by: Jiang, Xun, et al.
Published: (2025)

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction
by: Reimann, Lennart M., et al.
Published: (2024)

Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal
by: Jiang, Wenqi, et al.
Published: (2024)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
by: Zelioli, Enrico, et al.
Published: (2024)

PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator
by: Harary, Yuval, et al.
Published: (2026)

Computing with Clocks
by: Edwards, Jonathan, et al.
Published: (2024)

On the Excitability of Ultra-Low-Power CMOS Analog Spiking Neurons
by: Van Brandt, Léopold, et al.
Published: (2025)

An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion
by: Pedroso, Paolo, et al.
Published: (2026)

Content Addressable Memory Design with Reference Resistor for Improved Search Resolution
by: Narla, Siri, et al.
Published: (2025)

Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
by: Kumar, Aman, et al.
Published: (2024)

Utilizing Layout Effects for Analog Logic Locking
by: Aljafar, Muayad J., et al.
Published: (2024)

The Impact of Logic Locking on Confidentiality: An Automated Evaluation
by: Reimann, Lennart M., et al.
Published: (2025)

Prime+Retouch: When Cache is Locked and Leaked
by: Lee, Jaehyuk, et al.
Published: (2024)