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| Main Authors: | , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2501.14815 |
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| _version_ | 1866915124205322240 |
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| author | Cho, Shenghsun Patel, Mrunal Kaladagi, Basavaraj Chen, Han Palit, Tapti Ferdman, Michael Milder, Peter |
| author_facet | Cho, Shenghsun Patel, Mrunal Kaladagi, Basavaraj Chen, Han Palit, Tapti Ferdman, Michael Milder, Peter |
| contents | PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_14815 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs Cho, Shenghsun Patel, Mrunal Kaladagi, Basavaraj Chen, Han Palit, Tapti Ferdman, Michael Milder, Peter Distributed, Parallel, and Cluster Computing Artificial Intelligence Hardware Architecture Networking and Internet Architecture PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations. |
| title | A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs |
| topic | Distributed, Parallel, and Cluster Computing Artificial Intelligence Hardware Architecture Networking and Internet Architecture |
| url | https://arxiv.org/abs/2501.14815 |