A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
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arXiv
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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866911030915891200 |
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| author | Galimberti, Andrea Montanaro, Gabriele Motta, Andrea Proverbio, Federico Zoni, Davide |
| author_facet | Galimberti, Andrea Montanaro, Gabriele Motta, Andrea Proverbio, Federico Zoni, Davide |
| contents | FPGAs are increasingly utilized in data centers due to their capacity to exploit data parallelism in computationally intensive workloads. Furthermore, the processing of modern data center workloads requires moving vast amounts of data, making it essential to optimize data exchange between FPGAs and memory. This paper introduces a novel benchmarking platform for the evaluation of DDR4 memory performance in data-center-class FPGAs. The proposed solution features highly configurable traffic generation with complex memory access patterns defined at run time and can be flexibly instantiated on the target FPGA to support multiple memory channels and varying data rates. An extensive experimental campaign, targeting the AMD Kintex UltraScale 115 FPGA and encompassing up to three memory channels with data rates ranging from 1600 to 2400 MT/s and various memory traffic configurations, demonstrates the benchmarking platform's capability to effectively evaluate DDR4 memory performance. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_15582 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs Galimberti, Andrea Montanaro, Gabriele Motta, Andrea Proverbio, Federico Zoni, Davide Hardware Architecture FPGAs are increasingly utilized in data centers due to their capacity to exploit data parallelism in computationally intensive workloads. Furthermore, the processing of modern data center workloads requires moving vast amounts of data, making it essential to optimize data exchange between FPGAs and memory. This paper introduces a novel benchmarking platform for the evaluation of DDR4 memory performance in data-center-class FPGAs. The proposed solution features highly configurable traffic generation with complex memory access patterns defined at run time and can be flexibly instantiated on the target FPGA to support multiple memory channels and varying data rates. An extensive experimental campaign, targeting the AMD Kintex UltraScale 115 FPGA and encompassing up to three memory channels with data rates ranging from 1600 to 2400 MT/s and various memory traffic configurations, demonstrates the benchmarking platform's capability to effectively evaluate DDR4 memory performance. |
| title | A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2501.15582 |