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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2501.18113 |
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| _version_ | 1866929694817910784 |
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| author | Kurzynski, Marco Sinclair, Matthew D. |
| author_facet | Kurzynski, Marco Sinclair, Matthew D. |
| contents | In this work we have enhanced gem5's GPU model support to add Matrix Core Engines (MCEs). Specifically, on the AMD MI200 and MI300 GPUs that gem5 supports, these MCEs perform Matrix Fused Multiply Add (MFMA) instructions for a variety of precisions. By adding this support, our changes enable running state-of-the-art ML workloads in gem5, as well as examining how MCE optimizations impact the behavior of future systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_18113 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Adding MFMA Support to gem5 Kurzynski, Marco Sinclair, Matthew D. Hardware Architecture In this work we have enhanced gem5's GPU model support to add Matrix Core Engines (MCEs). Specifically, on the AMD MI200 and MI300 GPUs that gem5 supports, these MCEs perform Matrix Fused Multiply Add (MFMA) instructions for a variety of precisions. By adding this support, our changes enable running state-of-the-art ML workloads in gem5, as well as examining how MCE optimizations impact the behavior of future systems. |
| title | Adding MFMA Support to gem5 |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2501.18113 |