Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2501.18169 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866915129340198912 |
|---|---|
| author | Kumar, Abhishek Vijaya Devraj, Arjun Bunandar, Darius Singh, Rachee |
| author_facet | Kumar, Abhishek Vijaya Devraj, Arjun Bunandar, Darius Singh, Rachee |
| contents | We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_18169 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Chip-to-chip photonic connectivity in multi-accelerator servers for ML Kumar, Abhishek Vijaya Devraj, Arjun Bunandar, Darius Singh, Rachee Networking and Internet Architecture We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput. |
| title | Chip-to-chip photonic connectivity in multi-accelerator servers for ML |
| topic | Networking and Internet Architecture |
| url | https://arxiv.org/abs/2501.18169 |