An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator
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arXiv
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| Format: | Preprint |
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2025
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| author | Tunheim, Svein Anders Zheng, Yujin Jiao, Lei Shafik, Rishad Yakovlev, Alex Granmo, Ole-Christoffer |
| author_facet | Tunheim, Svein Anders Zheng, Yujin Jiao, Lei Shafik, Rishad Yakovlev, Alex Granmo, Ole-Christoffer |
| contents | We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28$\times$28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm$^2$. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 $μ$s which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2501_19347 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator Tunheim, Svein Anders Zheng, Yujin Jiao, Lei Shafik, Rishad Yakovlev, Alex Granmo, Ole-Christoffer Machine Learning Hardware Architecture B.7 We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28$\times$28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm$^2$. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 $μ$s which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models. |
| title | An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator |
| topic | Machine Learning Hardware Architecture B.7 |
| url | https://arxiv.org/abs/2501.19347 |