Theoretical complexity analysis of many-cores on a single chip
Fuente:
arXiv
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866913673797173248 |
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| author | Ginosar, Ran |
| author_facet | Ginosar, Ran |
| contents | When a single core is scaled up to m cores occupying the same chip area and executing the same (parallelizable) task, achievable speedup is square-root m, power is reduced by square-root m and energy is reduced by m. Thus, many-core architectures can efficiently outperform architectures of a single core and a small-count multi-core. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_00153 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Theoretical complexity analysis of many-cores on a single chip Ginosar, Ran Hardware Architecture When a single core is scaled up to m cores occupying the same chip area and executing the same (parallelizable) task, achievable speedup is square-root m, power is reduced by square-root m and energy is reduced by m. Thus, many-core architectures can efficiently outperform architectures of a single core and a small-count multi-core. |
| title | Theoretical complexity analysis of many-cores on a single chip |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2502.00153 |