Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends
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arXiv
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| Main Authors: | Schneider, Ian, Xu, Hui, Benecke, Stephan, Patterson, David, Huang, Keguo, Ranganathan, Parthasarathy, Elsworth, Cooper |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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