Cover Image

Hardware and software build flow with SoCMake

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Pejašinović, Risto, Caratelli, Alessandro, Nookala, Anvesh, Denkinger, Benoît Walter, Andorno, Marco
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
by: Tirelli, Cristian, et al.
Published: (2024)

Synapse: Virtualizing Match Tables in Programmable Hardware
by: Lahmer, Seyyidahmed, et al.
Published: (2025)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)

Sustainable Hardware Specialization
by: Dangi, Pranav, et al.
Published: (2024)

TOP: Towards Open & Predictable Heterogeneous SoCs
by: Valente, Luca, et al.
Published: (2024)

IMS: Intelligent Hardware Monitoring System for Secure SoCs
by: Foudhaili, Wadid, et al.
Published: (2026)

Teardown Analysis of Samsung S20 Exynos 990 SoC
by: Jadoon, Nabeel Ahmad Khan, et al.
Published: (2025)

A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing
by: Beyene, Abel, et al.
Published: (2025)

Analyzing and Improving Hardware Modeling of Accel-Sim
by: Huerta, Rodrigo, et al.
Published: (2024)

QED: Scalable Verification of Hardware Memory Consistency
by: Ravi, Gokulan, et al.
Published: (2024)

NeuroVM: Dynamic Neuromorphic Hardware Virtualization
by: Isik, Murat, et al.
Published: (2024)

In-Memory Computing Architecture for Efficient Hardware Security
by: Ajmi, Hala, et al.
Published: (2024)

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
by: Kumar, Vineet, et al.
Published: (2025)

SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
by: Cai, Jingwei, et al.
Published: (2025)

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
by: Leon, Vasileios, et al.
Published: (2025)

Domain-specific Hardware Acceleration for Model Predictive Path Integral Control
by: Tanguy-Legac, Erwan, et al.
Published: (2026)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)

Hardware-Aware DNN Compression for Homogeneous Edge Devices
by: Zhang, Kunlong, et al.
Published: (2025)

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration
by: Shahawy, Mohamed, et al.
Published: (2025)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)

An Efficient Sparse Hardware Accelerator for Spike-Driven Transformer
by: Li, Zhengke, et al.
Published: (2025)

Look-Up Table based Neural Network Hardware
by: Sen, Ovishake, et al.
Published: (2024)

Direct Integer Division in RNS and its Hardware Solutions
by: Olsen, Eric B.
Published: (2026)

Closing the Gap Between Float and Posit Hardware Efficiency
by: Jonnalagadda, Aditya Anirudh, et al.
Published: (2026)

A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)

Hardware for converting floating-point to the microscaling (MX) format
by: Gorodecky, Danila, et al.
Published: (2024)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
by: Koenig, Cyril, et al.
Published: (2025)

A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
by: Montanaro, Gabriele, et al.
Published: (2024)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
by: Popovici, Doru Thom, et al.
Published: (2025)

Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA
by: Ando, Takuto, et al.
Published: (2025)

Hardware Acceleration in Portable MRIs: State of the Art and Future Prospects
by: Habsi, Omar Al, et al.
Published: (2025)

HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
by: Agarwal, Ayushi, et al.
Published: (2026)

Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
by: Ramsauer, Ralf, et al.
Published: (2022)

Taming Performance Variability caused by Client-Side Hardware Configuration
by: Antoniou, Georgia, et al.
Published: (2024)

Xpikeformer: Hybrid Analog-Digital Hardware Acceleration for Spiking Transformers
by: Song, Zihang, et al.
Published: (2024)

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
by: Schmulbach, Viansa, et al.
Published: (2025)

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
by: Jung, Victor J. B., et al.
Published: (2025)

Apple vs. Oranges: Evaluating the Apple Silicon M-Series SoCs for HPC Performance and Efficiency
by: Hübner, Paul, et al.
Published: (2025)

From Circuits to SoC Processors: Arithmetic Approximation Techniques & Embedded Computing Methodologies for DSP Acceleration
by: Leon, Vasileios
Published: (2023)