Toward Automated Potential Primary Asset Identification in Verilog Designs
Fuente:
arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866913884316631040 |
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| author | Nath, Subroto Kumer Deb Tan, Benjamin |
| author_facet | Nath, Subroto Kumer Deb Tan, Benjamin |
| contents | With greater design complexity, the challenge to anticipate and mitigate security issues provides more responsibility for the designer. As hardware provides the foundation of a secure system, we need tools and techniques that support engineers to improve trust and help them address security concerns. Knowing the security assets in a design is fundamental to downstream security analyses, such as threat modeling, weakness identification, and verification. This paper proposes an automated approach for the initial identification of potential security assets in a Verilog design. Taking inspiration from manual asset identification methodologies, we analyze open-source hardware designs in three IP families and identify patterns and commonalities likely to indicate structural assets. Through iterative refinement, we provide a potential set of primary security assets and thus help to reduce the manual search space. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_04648 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Toward Automated Potential Primary Asset Identification in Verilog Designs Nath, Subroto Kumer Deb Tan, Benjamin Cryptography and Security With greater design complexity, the challenge to anticipate and mitigate security issues provides more responsibility for the designer. As hardware provides the foundation of a secure system, we need tools and techniques that support engineers to improve trust and help them address security concerns. Knowing the security assets in a design is fundamental to downstream security analyses, such as threat modeling, weakness identification, and verification. This paper proposes an automated approach for the initial identification of potential security assets in a Verilog design. Taking inspiration from manual asset identification methodologies, we analyze open-source hardware designs in three IP families and identify patterns and commonalities likely to indicate structural assets. Through iterative refinement, we provide a potential set of primary security assets and thus help to reduce the manual search space. |
| title | Toward Automated Potential Primary Asset Identification in Verilog Designs |
| topic | Cryptography and Security |
| url | https://arxiv.org/abs/2502.04648 |