Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866909485527728128 |
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| author | Wei, Ying-Hao Wan, Zishen Crafton, Brian Spetalnick, Samuel Raychowdhury, Arijit |
| author_facet | Wei, Ying-Hao Wan, Zishen Crafton, Brian Spetalnick, Samuel Raychowdhury, Arijit |
| contents | With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a critical concern. This study confronts this challenge by introducing a detailed model that incorporates noise factors arising from both ADCs and RRAM devices. The experimental data is derived from a 40nm foundry RRAM test-chip, wherein different reference voltage configurations are applied, each tailored to its respective module. The mean and standard deviation values of HRS and LRS cells are derived through a randomized vector, forming the foundation for noise simulation within our analytical framework. Additionally, the study examines the read-disturb effects, shedding light on the potential for accuracy deterioration in neural networks due to extended exposure to high-voltage stress. This phenomenon is mitigated through the proposed low-voltage read mode. Leveraging our derived comprehensive fault model from the RRAM test-chip, we evaluate CIM noise impact on both supervised learning (time-independent) and reinforcement learning (time-dependent) tasks, and demonstrate the effectiveness of reference tuning to mitigate noise impacts. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_05948 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory Wei, Ying-Hao Wan, Zishen Crafton, Brian Spetalnick, Samuel Raychowdhury, Arijit Emerging Technologies With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a critical concern. This study confronts this challenge by introducing a detailed model that incorporates noise factors arising from both ADCs and RRAM devices. The experimental data is derived from a 40nm foundry RRAM test-chip, wherein different reference voltage configurations are applied, each tailored to its respective module. The mean and standard deviation values of HRS and LRS cells are derived through a randomized vector, forming the foundation for noise simulation within our analytical framework. Additionally, the study examines the read-disturb effects, shedding light on the potential for accuracy deterioration in neural networks due to extended exposure to high-voltage stress. This phenomenon is mitigated through the proposed low-voltage read mode. Leveraging our derived comprehensive fault model from the RRAM test-chip, we evaluate CIM noise impact on both supervised learning (time-independent) and reinforcement learning (time-dependent) tasks, and demonstrate the effectiveness of reference tuning to mitigate noise impacts. |
| title | Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2502.05948 |