SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest

Fuente: arXiv
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Autores principales: Erhardt, Jack, Li, Ziang, Pinkham, Reid, Berkovich, Andrew, Zhang, Zhengya
Formato: Preprint
Publicado: 2025
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author Erhardt, Jack
Li, Ziang
Pinkham, Reid
Berkovich, Andrew
Zhang, Zhengya
author_facet Erhardt, Jack
Li, Ziang
Pinkham, Reid
Berkovich, Andrew
Zhang, Zhengya
contents Machine learning algorithms have enabled high quality stereo depth estimation to run on Augmented and Virtual Reality (AR/VR) devices. However, high energy consumption across the full image processing stack prevents stereo depth algorithms from running effectively on battery-limited devices. This paper introduces SteROI-D, a full stereo depth system paired with a mapping methodology. SteROI-D exploits Region-of-Interest (ROI) and temporal sparsity at the system level to save energy. SteROI-D's flexible and heterogeneous compute fabric supports diverse ROIs. Importantly, we introduce a systematic mapping methodology to effectively handle dynamic ROIs, thereby maximizing energy savings. Using these techniques, our 28nm prototype SteROI-D design achieves up to 4.35x reduction in total system energy compared to a baseline ASIC.
format Preprint
id arxiv_https___arxiv_org_abs_2502_09528
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest
Erhardt, Jack
Li, Ziang
Pinkham, Reid
Berkovich, Andrew
Zhang, Zhengya
Computer Vision and Pattern Recognition
Hardware Architecture
Machine learning algorithms have enabled high quality stereo depth estimation to run on Augmented and Virtual Reality (AR/VR) devices. However, high energy consumption across the full image processing stack prevents stereo depth algorithms from running effectively on battery-limited devices. This paper introduces SteROI-D, a full stereo depth system paired with a mapping methodology. SteROI-D exploits Region-of-Interest (ROI) and temporal sparsity at the system level to save energy. SteROI-D's flexible and heterogeneous compute fabric supports diverse ROIs. Importantly, we introduce a systematic mapping methodology to effectively handle dynamic ROIs, thereby maximizing energy savings. Using these techniques, our 28nm prototype SteROI-D design achieves up to 4.35x reduction in total system energy compared to a baseline ASIC.
title SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest
topic Computer Vision and Pattern Recognition
Hardware Architecture
url https://arxiv.org/abs/2502.09528