LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866916617283174400 |
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| author | Fang, Zhigang Chen, Renzhi Yang, Zhijie Guo, Yang Dai, Huadong Wang, Lei |
| author_facet | Fang, Zhigang Chen, Renzhi Yang, Zhijie Guo, Yang Dai, Huadong Wang, Lei |
| contents | Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redundant defect reports. Recent advancements in large language models (LLM) have introduced new possibilities in this area. In this paper, we propose LintLLM, an open-source Linting framework that utilizes LLMs to detect defects in Verilog code via Prompt of Logic-Tree and Defect Tracker. Furthermore, we create an open-source benchmark using the mutation-based defect injection technique to evaluate LLM's ability in detecting Verilog defects. Experimental results show that o1-mini improves the correct rate by 18.89\% and reduces the false-positive rate by 15.56\% compared with the best-performing EDA tool. Simultaneously, LintLLM operates at less than one-tenth of the cost of commercial EDA tools. This study demonstrates the potential of LLM as an efficient and cost-effective Linting tool for hardware design. The benchmark and experimental results are open-source at URL: https://github.com/fangzhigang32/Static-Verilog-Analysis |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_10815 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models Fang, Zhigang Chen, Renzhi Yang, Zhijie Guo, Yang Dai, Huadong Wang, Lei Hardware Architecture Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redundant defect reports. Recent advancements in large language models (LLM) have introduced new possibilities in this area. In this paper, we propose LintLLM, an open-source Linting framework that utilizes LLMs to detect defects in Verilog code via Prompt of Logic-Tree and Defect Tracker. Furthermore, we create an open-source benchmark using the mutation-based defect injection technique to evaluate LLM's ability in detecting Verilog defects. Experimental results show that o1-mini improves the correct rate by 18.89\% and reduces the false-positive rate by 15.56\% compared with the best-performing EDA tool. Simultaneously, LintLLM operates at less than one-tenth of the cost of commercial EDA tools. This study demonstrates the potential of LLM as an efficient and cost-effective Linting tool for hardware design. The benchmark and experimental results are open-source at URL: https://github.com/fangzhigang32/Static-Verilog-Analysis |
| title | LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2502.10815 |