Enabling Efficient Transaction Processing on CXL-Based Memory Sharing
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arXiv
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| Auteurs principaux: | , , , , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866911071355273216 |
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| author | Wang, Zhao Chen, Yiqi Li, Cong Niu, Dimin Guan, Tianchan Du, Zhaoyang Wei, Xingda Sun, Guangyu |
| author_facet | Wang, Zhao Chen, Yiqi Li, Cong Niu, Dimin Guan, Tianchan Du, Zhaoyang Wei, Xingda Sun, Guangyu |
| contents | Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute Express Link (CXL) as a network alternative, which enables low-latency and cache-coherent shared memory accesses. However, directly adopting standard CXL primitives leads to performance degradation due to the high cost of maintaining cross-node cache coherence. To address the CXL challenges, this paper introduces CtXnL, a software-hardware co-designed system that implements a novel hybrid coherence primitive tailored to the loosely coherent nature of transactional data. The core innovation of CtXnL is empowering transaction system developers with the ability to selectively achieve data coherence. Our evaluations on OLTP workloads demonstrate that CtXnL enhances performance, outperforming current network-based systems and achieves with up to 2.08x greater throughput than vanilla CXL memory sharing architectures across universal transaction processing policies. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_11046 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Enabling Efficient Transaction Processing on CXL-Based Memory Sharing Wang, Zhao Chen, Yiqi Li, Cong Niu, Dimin Guan, Tianchan Du, Zhaoyang Wei, Xingda Sun, Guangyu Hardware Architecture Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute Express Link (CXL) as a network alternative, which enables low-latency and cache-coherent shared memory accesses. However, directly adopting standard CXL primitives leads to performance degradation due to the high cost of maintaining cross-node cache coherence. To address the CXL challenges, this paper introduces CtXnL, a software-hardware co-designed system that implements a novel hybrid coherence primitive tailored to the loosely coherent nature of transactional data. The core innovation of CtXnL is empowering transaction system developers with the ability to selectively achieve data coherence. Our evaluations on OLTP workloads demonstrate that CtXnL enhances performance, outperforming current network-based systems and achieves with up to 2.08x greater throughput than vanilla CXL memory sharing architectures across universal transaction processing policies. |
| title | Enabling Efficient Transaction Processing on CXL-Based Memory Sharing |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2502.11046 |