Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory
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arXiv
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| Format: | Preprint |
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2025
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| author | Shi, Daijing Zhu, Yihang Fan, Anjunyi Tao, Yaoyu Yang, Yuchao Yan, Bonan |
| author_facet | Shi, Daijing Zhu, Yihang Fan, Anjunyi Tao, Yaoyu Yang, Yuchao Yan, Bonan |
| contents | Processing-in-memory (PIM) based on emerging devices such as memristors is more vulnerable to noise than traditional memories, due to the physical non-idealities and complex operations in analog domains. To ensure high reliability, efficient error-correcting code (ECC) is highly desired. However, state-of-the-art ECC schemes for PIM suffer drawbacks including dataflow interruptions, low code rates, and limited error correction patterns. In this work, we propose non-binary low-density parity-check (NB-LDPC) error correction running over the Galois field. Such NB-LDPC scheme with a long word length of 1024 bits can correct up to 8-bit errors with a code rate over 88%. Nonbinary GF operations can support both memory mode and PIM mode even with multi-level memory cells. We fabricate a 40nm prototype PIM chip equipped with our proposed NB-LDPC scheme for validation purposes. Experiments show that PIM with NB-LDPC error correction demonstrates up to 59.65 times bit error rate (BER) improvement over the original PIM without such error correction. The test chip delivers 2.978 times power efficiency enhancement over prior works. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_11487 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory Shi, Daijing Zhu, Yihang Fan, Anjunyi Tao, Yaoyu Yang, Yuchao Yan, Bonan Hardware Architecture Information Theory Processing-in-memory (PIM) based on emerging devices such as memristors is more vulnerable to noise than traditional memories, due to the physical non-idealities and complex operations in analog domains. To ensure high reliability, efficient error-correcting code (ECC) is highly desired. However, state-of-the-art ECC schemes for PIM suffer drawbacks including dataflow interruptions, low code rates, and limited error correction patterns. In this work, we propose non-binary low-density parity-check (NB-LDPC) error correction running over the Galois field. Such NB-LDPC scheme with a long word length of 1024 bits can correct up to 8-bit errors with a code rate over 88%. Nonbinary GF operations can support both memory mode and PIM mode even with multi-level memory cells. We fabricate a 40nm prototype PIM chip equipped with our proposed NB-LDPC scheme for validation purposes. Experiments show that PIM with NB-LDPC error correction demonstrates up to 59.65 times bit error rate (BER) improvement over the original PIM without such error correction. The test chip delivers 2.978 times power efficiency enhancement over prior works. |
| title | Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory |
| topic | Hardware Architecture Information Theory |
| url | https://arxiv.org/abs/2502.11487 |