Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators
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arXiv
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866917986564046848 |
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| author | Liu, Qunyou Zapater, Marina Atienza, David |
| author_facet | Liu, Qunyou Zapater, Marina Atienza, David |
| contents | The growing demand for efficient, high-performance processing in machine learning (ML) and image processing has made hardware accelerators, such as GPUs and Data Streaming Accelerators (DSAs), increasingly essential. These accelerators enhance ML and image processing tasks by offloading computation from the CPU to dedicated hardware. These accelerators rely on interconnects for efficient data transfer, making interconnect design crucial for system-level performance. This paper introduces Gem5-AcceSys, an innovative framework for system-level exploration of standard interconnects and configurable memory hierarchies. Using a matrix multiplication accelerator tailored for transformer workloads as a case study, we evaluate PCIe performance across diverse memory types (DDR4, DDR5, GDDR6, HBM2) and configurations, including host-side and device-side memory. Our findings demonstrate that optimized interconnects can achieve up to 80% of device-side memory performance and, in some scenarios, even surpass it. These results offer actionable insights for system architects, enabling a balanced approach to performance and cost in next-generation accelerator design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_12273 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators Liu, Qunyou Zapater, Marina Atienza, David Hardware Architecture Performance The growing demand for efficient, high-performance processing in machine learning (ML) and image processing has made hardware accelerators, such as GPUs and Data Streaming Accelerators (DSAs), increasingly essential. These accelerators enhance ML and image processing tasks by offloading computation from the CPU to dedicated hardware. These accelerators rely on interconnects for efficient data transfer, making interconnect design crucial for system-level performance. This paper introduces Gem5-AcceSys, an innovative framework for system-level exploration of standard interconnects and configurable memory hierarchies. Using a matrix multiplication accelerator tailored for transformer workloads as a case study, we evaluate PCIe performance across diverse memory types (DDR4, DDR5, GDDR6, HBM2) and configurations, including host-side and device-side memory. Our findings demonstrate that optimized interconnects can achieve up to 80% of device-side memory performance and, in some scenarios, even surpass it. These results offer actionable insights for system architects, enabling a balanced approach to performance and cost in next-generation accelerator design. |
| title | Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators |
| topic | Hardware Architecture Performance |
| url | https://arxiv.org/abs/2502.12273 |