APA-Zitierstil (7. Ausg.)

Wu, H., Zheng, H., Pu, Y., & Yu, B. (2025). Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.

Chicago-Zitierstil (17. Ausg.)

Wu, Haoyuan, Haisheng Zheng, Yuan Pu, und Bei Yu. Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment. 2025.

MLA-Zitierstil (9. Ausg.)

Wu, Haoyuan, et al. Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment. 2025.