FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866929724989636608 |
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| author | Chaudhuri, Jayeeta Nassar, Hassan Gnad, Dennis R. E. Henkel, Jorg Tahoori, Mehdi B. Chakrabarty, Krishnendu |
| author_facet | Chaudhuri, Jayeeta Nassar, Hassan Gnad, Dennis R. E. Henkel, Jorg Tahoori, Mehdi B. Chakrabarty, Krishnendu |
| contents | Modern FPGAs are increasingly supporting multi-tenancy to enable dynamic reconfiguration of user modules. While multi-tenant FPGAs improve utilization and flexibility, this paradigm introduces critical security threats. In this paper, we present FLARE, a fault attack that exploits vulnerabilities in the partial reconfiguration process, specifically while a user bitstream is being uploaded to the FPGA by a reconfiguration manager. Unlike traditional fault attacks that operate during module runtime, FLARE injects faults in the bitstream during its reconfiguration, altering the configuration address and redirecting it to unintended partial reconfigurable regions (PRRs). This enables the overwriting of pre-configured co-tenant modules, disrupting their functionality. FLARE leverages power-wasters that activate briefly during the reconfiguration process, making the attack stealthy and more challenging to detect with existing countermeasures. Experimental results on a Xilinx Pynq FPGA demonstrate the effectiveness of FLARE in compromising multiple user bitstreams during the reconfiguration process. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_15578 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs Chaudhuri, Jayeeta Nassar, Hassan Gnad, Dennis R. E. Henkel, Jorg Tahoori, Mehdi B. Chakrabarty, Krishnendu Cryptography and Security Modern FPGAs are increasingly supporting multi-tenancy to enable dynamic reconfiguration of user modules. While multi-tenant FPGAs improve utilization and flexibility, this paradigm introduces critical security threats. In this paper, we present FLARE, a fault attack that exploits vulnerabilities in the partial reconfiguration process, specifically while a user bitstream is being uploaded to the FPGA by a reconfiguration manager. Unlike traditional fault attacks that operate during module runtime, FLARE injects faults in the bitstream during its reconfiguration, altering the configuration address and redirecting it to unintended partial reconfigurable regions (PRRs). This enables the overwriting of pre-configured co-tenant modules, disrupting their functionality. FLARE leverages power-wasters that activate briefly during the reconfiguration process, making the attack stealthy and more challenging to detect with existing countermeasures. Experimental results on a Xilinx Pynq FPGA demonstrate the effectiveness of FLARE in compromising multiple user bitstreams during the reconfiguration process. |
| title | FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs |
| topic | Cryptography and Security |
| url | https://arxiv.org/abs/2502.15578 |