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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2502.16334 |
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| _version_ | 1866912570909130752 |
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| author | Robitaille, Tristan Liu, Xilin |
| author_facet | Robitaille, Tristan Liu, Xilin |
| contents | This paper presents SleepViT, a custom accelerator ASIC for real-time, low-power sleep stage classification in wearable devices. At the core of SleepViT is a lightweight vision transformer model specifically optimized for electroencephalogram (EEG)-based sleep stage classification. The model is trained on the MASS SS3 dataset and achieves a classification accuracy of 82.9% across four sleep stages, while requiring only 31.6k weights-demonstrating its suitability for embedded inference. The proposed transformer is designed and synthesized in 65nm CMOS technology. To minimize power and area, the architecture adopts a novel layer-dependent fixed-point quantization scheme, variable data widths, and optimized memory access patterns. The synthesized accelerator occupies 0.754mm2 of silicon, operates at a maximum clock frequency of 379MHz, and consumes 6.54mW dynamic and 11.0mW leakage power over a 45.6ms inference window. With aggressive power gating during idle periods, the effective average power is 0.56mW, enabling extended battery life in wearable devices. This work highlights the feasibility of deploying transformer-based models in highly constrained edge environments and provides a pathway for future biomedical ASICs that require both real-time performance and ultra-low power consumption. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_16334 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Vision Transformer Accelerator ASIC for Real-Time Low-Power Sleep Staging Robitaille, Tristan Liu, Xilin Signal Processing This paper presents SleepViT, a custom accelerator ASIC for real-time, low-power sleep stage classification in wearable devices. At the core of SleepViT is a lightweight vision transformer model specifically optimized for electroencephalogram (EEG)-based sleep stage classification. The model is trained on the MASS SS3 dataset and achieves a classification accuracy of 82.9% across four sleep stages, while requiring only 31.6k weights-demonstrating its suitability for embedded inference. The proposed transformer is designed and synthesized in 65nm CMOS technology. To minimize power and area, the architecture adopts a novel layer-dependent fixed-point quantization scheme, variable data widths, and optimized memory access patterns. The synthesized accelerator occupies 0.754mm2 of silicon, operates at a maximum clock frequency of 379MHz, and consumes 6.54mW dynamic and 11.0mW leakage power over a 45.6ms inference window. With aggressive power gating during idle periods, the effective average power is 0.56mW, enabling extended battery life in wearable devices. This work highlights the feasibility of deploying transformer-based models in highly constrained edge environments and provides a pathway for future biomedical ASICs that require both real-time performance and ultra-low power consumption. |
| title | Vision Transformer Accelerator ASIC for Real-Time Low-Power Sleep Staging |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2502.16334 |