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Main Authors: Romano, Giuseppe, Jain, Aakrati, Dehmamy, Nima, Chi, Cheng, Zhang, Xin
Format: Preprint
Published: 2025
Subjects:
Online Access:https://arxiv.org/abs/2502.16633
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author Romano, Giuseppe
Jain, Aakrati
Dehmamy, Nima
Chi, Cheng
Zhang, Xin
author_facet Romano, Giuseppe
Jain, Aakrati
Dehmamy, Nima
Chi, Cheng
Zhang, Xin
contents Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring careful floorplanning to ensure efficient heat distribution. To address thermal considerations, layout optimization algorithms concurrently minimize the total wirelength and the maximum temperature. However, these efforts employ gradient-free approaches, such as simulated annealing, which suffer from poor scaling and slow convergence. In this paper, we propose DiffChip, a chiplet placement algorithm based on automatic differentiation (AD). The proposed framework relies on a differentiable thermal solver that computes the sensitivity of the temperature map with respect to the positions of the chiplets. Regularization strategies for peak temperature, heat sources, and material properties enable end-to-end differentiability, allowing for gradient-based optimization. We apply DiffChip to optimize a layout where the total wirelength is minimized while keeping the maximum temperature below a desired threshold. By leveraging AD and physics-aware optimization, our approach accelerates the design process of microelectronic systems, exceeding traditional trial-and-error and gradient-free methods.
format Preprint
id arxiv_https___arxiv_org_abs_2502_16633
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle DiffChip: Thermally Aware Chip Placement with Automatic Differentiation
Romano, Giuseppe
Jain, Aakrati
Dehmamy, Nima
Chi, Cheng
Zhang, Xin
Computational Physics
Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring careful floorplanning to ensure efficient heat distribution. To address thermal considerations, layout optimization algorithms concurrently minimize the total wirelength and the maximum temperature. However, these efforts employ gradient-free approaches, such as simulated annealing, which suffer from poor scaling and slow convergence. In this paper, we propose DiffChip, a chiplet placement algorithm based on automatic differentiation (AD). The proposed framework relies on a differentiable thermal solver that computes the sensitivity of the temperature map with respect to the positions of the chiplets. Regularization strategies for peak temperature, heat sources, and material properties enable end-to-end differentiability, allowing for gradient-based optimization. We apply DiffChip to optimize a layout where the total wirelength is minimized while keeping the maximum temperature below a desired threshold. By leveraging AD and physics-aware optimization, our approach accelerates the design process of microelectronic systems, exceeding traditional trial-and-error and gradient-free methods.
title DiffChip: Thermally Aware Chip Placement with Automatic Differentiation
topic Computational Physics
url https://arxiv.org/abs/2502.16633