A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
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| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866909511954989056 |
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| author | Garofalo, Angelo Ottaviano, Alessandro Perotti, Matteo Benz, Thomas Tortorella, Yvan Balas, Robert Rogenmoser, Michael Zhang, Chi Bertaccini, Luca Wistoff, Nils Ciani, Maicol Koenig, Cyril Sinigaglia, Mattia Valente, Luca Scheffler, Paul Eggimann, Manuel Cavalcante, Matheus Restuccia, Francesco Biondi, Alessandro Conti, Francesco Gurkaynak, Frank K. Rossi, Davide Benini, Luca |
| author_facet | Garofalo, Angelo Ottaviano, Alessandro Perotti, Matteo Benz, Thomas Tortorella, Yvan Balas, Robert Rogenmoser, Michael Zhang, Chi Bertaccini, Luca Wistoff, Nils Ciani, Maicol Koenig, Cyril Sinigaglia, Mattia Valente, Luca Scheffler, Paul Eggimann, Manuel Cavalcante, Matheus Restuccia, Francesco Biondi, Alessandro Conti, Francesco Gurkaynak, Frank K. Rossi, Davide Benini, Luca |
| contents | Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges, in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm2. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_18953 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications Garofalo, Angelo Ottaviano, Alessandro Perotti, Matteo Benz, Thomas Tortorella, Yvan Balas, Robert Rogenmoser, Michael Zhang, Chi Bertaccini, Luca Wistoff, Nils Ciani, Maicol Koenig, Cyril Sinigaglia, Mattia Valente, Luca Scheffler, Paul Eggimann, Manuel Cavalcante, Matheus Restuccia, Francesco Biondi, Alessandro Conti, Francesco Gurkaynak, Frank K. Rossi, Davide Benini, Luca Hardware Architecture Distributed, Parallel, and Cluster Computing Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ensuring reliable and time-predictable execution of critical tasks sharing resources with non-critical tasks, while also fitting within a sub-2W power envelope. To tackle these multi-dimensional challenges, in this brief, we present a 16nm, reliable, time-predictable heterogeneous SoC with multiple programmable accelerators. Within a 1.2W power envelope, the SoC integrates software-configurable hardware IPs to ensure predictable access to shared resources, such as the on-chip interconnect and memory system, leading to tight upper bounds on execution times of critical applications. To accelerate mixed-precision mission-critical AI, the SoC integrates a reliable multi-core accelerator achieving 304.9 GOPS peak performance at 1.6 TOPS/W energy efficiency. Non-critical, compute-intensive, floating-point workloads are accelerated by a dual-core vector cluster, achieving 121.8 GFLOPS at 1.1 TFLOPS/W and 106.8 GFLOPS/mm2. |
| title | A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications |
| topic | Hardware Architecture Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2502.18953 |