Evaluation of CGRA Toolchains
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arXiv
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| Autori principali: | , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866929733737906176 |
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| author | Walter, Dominik Halm, Marita Seidel, Daniel Ghosh, Indrayudh Heidorn, Christian Hannig, Frank Teich, Jürgen |
| author_facet | Walter, Dominik Halm, Marita Seidel, Daniel Ghosh, Indrayudh Heidorn, Christian Hannig, Frank Teich, Jürgen |
| contents | Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class for such accelerators are so-called processor arrays, which typically integrate a two-dimensional mesh of interconnected processing elements (PEs). Such arrays are specifically designed to accelerate the execution of multidimensional nested loops by exploiting the intrinsic parallelism of such loops. Coarse-grained reconfigurable arrays (CGRAs) belong to this class of accelerator architectures. In this work, we analyze four toolchains for mapping loop programs onto CGRAs and compare the resulting mappings wrt. performance, i.e., latency. While most toolchains succeed in simpler kernels like general matrix multiplication, some struggle to find valid mappings for more complex loops like a triangular solver. Furthermore, we observe that the considered CGRA mappers generally tend to underutilize the available PEs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2502_19114 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Evaluation of CGRA Toolchains Walter, Dominik Halm, Marita Seidel, Daniel Ghosh, Indrayudh Heidorn, Christian Hannig, Frank Teich, Jürgen Hardware Architecture Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class for such accelerators are so-called processor arrays, which typically integrate a two-dimensional mesh of interconnected processing elements (PEs). Such arrays are specifically designed to accelerate the execution of multidimensional nested loops by exploiting the intrinsic parallelism of such loops. Coarse-grained reconfigurable arrays (CGRAs) belong to this class of accelerator architectures. In this work, we analyze four toolchains for mapping loop programs onto CGRAs and compare the resulting mappings wrt. performance, i.e., latency. While most toolchains succeed in simpler kernels like general matrix multiplication, some struggle to find valid mappings for more complex loops like a triangular solver. Furthermore, we observe that the considered CGRA mappers generally tend to underutilize the available PEs. |
| title | Evaluation of CGRA Toolchains |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2502.19114 |