Cover Image

Wildcat: Educational RISC-V Microprocessors

Fuente: arXiv

Saved in:

Bibliographic Details
Main Author:	Schoeberl, Martin
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)

Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)

Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)

A Bespoke Design Approach to Low-Power Printed Microprocessors for Machine Learning Applications
by: Chaidos, Panagiotis, et al.
Published: (2025)

Support Vector Machines Classification on Bendable RISC-V
by: Vergos, Polykarpos, et al.
Published: (2025)

Efficient Implementation of RISC-V Vector Permutation Instructions
by: Titopoulos, Vasileios, et al.
Published: (2025)

ARISE: Automating RISC-V Instruction Set Extension
by: Hager-Clukas, Andreas, et al.
Published: (2025)

Runtime Energy Monitoring for RISC-V Soft-Cores
by: Scionti, Alberto, et al.
Published: (2025)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores
by: Djupdal, Asbjørn, et al.
Published: (2025)

Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
by: Ahmed, Sajjad, et al.
Published: (2026)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
by: Jacobs, Eino, et al.
Published: (2024)

Decoupled Control Flow and Data Access in RISC-V GPGPUs
by: Sarda, Giuseppe M., et al.
Published: (2025)

Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
by: Ramsauer, Ralf, et al.
Published: (2022)

Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)

Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)

Efficient Read-Port-Count Reduction Schemes for the Centralized Physical Register File in a Superscalar Microprocessor
by: Los, Denis
Published: (2025)

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
by: Narkthong, Nuntipat, et al.
Published: (2025)

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
by: Rezunov, Evgenii, et al.
Published: (2025)

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
by: Jiang, Limin, et al.
Published: (2025)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
by: Petrolo, Vincenzo, et al.
Published: (2025)

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
by: Laghi, Umberto, et al.
Published: (2025)

RISC-V processor enhanced with a dynamic micro-decoder unit
by: Pottier, Juliette, et al.
Published: (2024)

Branch Prediction in Hardcaml for a RISC-V 32im CPU
by: Saveau, Alex
Published: (2023)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
by: Caon, Michele, et al.
Published: (2024)

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
by: Delavari, Arvin, et al.
Published: (2024)

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges
by: Zhong, Xinchao, et al.
Published: (2024)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
by: Perotti, Matteo, et al.
Published: (2024)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration
by: Numan, Omar, et al.
Published: (2025)

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
by: Pu, Huanzhi, et al.
Published: (2025)

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
by: Koenig, Cyril, et al.
Published: (2025)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
by: Cammarata, Danilo, et al.
Published: (2025)

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
by: Kumar, Vineet, et al.
Published: (2025)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)