$R^4$: A Racetrack Register File with Runtime Software Reconfiguration
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866916635127840768 |
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| author | Hakert, Christian Chen, Shuo-Han Heider, Kay Kühn, Roland Chen, Yun-Chih Teubner, Jens Chen, Jian-Jia |
| author_facet | Hakert, Christian Chen, Shuo-Han Heider, Kay Kühn, Roland Chen, Yun-Chih Teubner, Jens Chen, Jian-Jia |
| contents | Arising disruptive memory technologies continuously make their way into the memory hierarchy at various levels. Racetrack memory is one promising candidate for future memory due to the overall low energy consumption, access latency and high endurance. However, the access dependent shift property of racetrack memory can make it easily a poor candidate, when the number of shifts is not properly reduced. Therefore, we explore how a register file can be constructed by using non-volatile racetrack memories with a properly reduced number of shifts. Our proposed architecture allows allocating registers in a horizontal or vertical allocation mode, where registers are either scattered across nanotracks or allocated along tracks. In this paper, we propose a dynamic approach, where the allocation can be altered at any access between horizontal and vertical. Control flow graph based static program analysis with simulation-based branch probabilities supplies crucially important recommendations for the dynamic allocation, which are applied at runtime. Experimental evaluation, including a custom gem5 simulation setup, reveals the need for this type of runtime reconfiguration.
While the performance in terms of energy consumption, for instance, can be comparably high as SRAM when no runtime reconfiguration is done, the dynamic approach reduces it by up to $\approx 6\times$. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2502_20775 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | $R^4$: A Racetrack Register File with Runtime Software Reconfiguration Hakert, Christian Chen, Shuo-Han Heider, Kay Kühn, Roland Chen, Yun-Chih Teubner, Jens Chen, Jian-Jia Hardware Architecture Emerging Technologies Arising disruptive memory technologies continuously make their way into the memory hierarchy at various levels. Racetrack memory is one promising candidate for future memory due to the overall low energy consumption, access latency and high endurance. However, the access dependent shift property of racetrack memory can make it easily a poor candidate, when the number of shifts is not properly reduced. Therefore, we explore how a register file can be constructed by using non-volatile racetrack memories with a properly reduced number of shifts. Our proposed architecture allows allocating registers in a horizontal or vertical allocation mode, where registers are either scattered across nanotracks or allocated along tracks. In this paper, we propose a dynamic approach, where the allocation can be altered at any access between horizontal and vertical. Control flow graph based static program analysis with simulation-based branch probabilities supplies crucially important recommendations for the dynamic allocation, which are applied at runtime. Experimental evaluation, including a custom gem5 simulation setup, reveals the need for this type of runtime reconfiguration. While the performance in terms of energy consumption, for instance, can be comparably high as SRAM when no runtime reconfiguration is done, the dynamic approach reduces it by up to $\approx 6\times$. |
| title | $R^4$: A Racetrack Register File with Runtime Software Reconfiguration |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2502.20775 |