Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Fuente:
arXiv
Saved in:
| Main Authors: | Zhou, Jie, Ji, Youshu, Wang, Ning, Hu, Yuchen, Jiao, Xinyao, Yao, Bingkun, Fang, Xinwei, Zhao, Shuai, Guan, Nan, Jiang, Zhe |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)
by: Hu, Yuchen, et al.
Published: (2024)
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
by: Wang, Ning, et al.
Published: (2025)
by: Wang, Ning, et al.
Published: (2025)
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025)
by: Ye, Junhao, et al.
Published: (2025)
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)
by: Ye, Junhao, et al.
Published: (2026)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
by: Wang, Ning, et al.
Published: (2024)
by: Wang, Ning, et al.
Published: (2024)
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
by: Wu, Fenghua, et al.
Published: (2025)
by: Wu, Fenghua, et al.
Published: (2025)
MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)
by: Xu, Ke, et al.
Published: (2024)
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
by: Maddala, Karthik, et al.
Published: (2024)
by: Maddala, Karthik, et al.
Published: (2024)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)
by: Wang, Ning, et al.
Published: (2025)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
by: Yao, Bingkun, et al.
Published: (2024)
by: Yao, Bingkun, et al.
Published: (2024)
From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
by: Wang, Yonghao, et al.
Published: (2026)
by: Wang, Yonghao, et al.
Published: (2026)
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)
by: Sun, Jialin, et al.
Published: (2025)
Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
by: Cai, Siyang, et al.
Published: (2026)
by: Cai, Siyang, et al.
Published: (2026)
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Yan, Zhiyuan, et al.
Published: (2024)
by: Yan, Zhiyuan, et al.
Published: (2024)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Fang, Wenji, et al.
Published: (2024)
by: Fang, Wenji, et al.
Published: (2024)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)
by: Fang, Wenji, et al.
Published: (2026)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)
by: Yin, Shuo, et al.
Published: (2026)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)
by: Deng, Chenhui, et al.
Published: (2026)
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
by: Mashnoor, Nowfel, et al.
Published: (2026)
by: Mashnoor, Nowfel, et al.
Published: (2026)
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)
by: Chao, Zhiteng, et al.
Published: (2025)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)
by: Allam, Ahmed, et al.
Published: (2024)
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)
by: Liu, Shang, et al.
Published: (2023)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
by: Zoni, Davide, et al.
Published: (2025)
by: Zoni, Davide, et al.
Published: (2025)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)
by: Deng, Chenhui, et al.
Published: (2025)
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)
by: Fang, Wenji, et al.
Published: (2024)
Assessing Large Language Models in Generating RTL Design Specifications
by: Huang, Hung-Ming, et al.
Published: (2025)
by: Huang, Hung-Ming, et al.
Published: (2025)
Correct Wrong Path
by: Godala, Bhargav Reddy, et al.
Published: (2024)
by: Godala, Bhargav Reddy, et al.
Published: (2024)
Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)
by: Bhattaram, Amulya, et al.
Published: (2025)
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
by: Wu, Yuchao, et al.
Published: (2026)
by: Wu, Yuchao, et al.
Published: (2026)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
by: Zhang, Jie, et al.
Published: (2026)
by: Zhang, Jie, et al.
Published: (2026)
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)
by: Li, Chengxi, et al.
Published: (2025)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
by: Sehm, Robin, et al.
Published: (2025)
by: Sehm, Robin, et al.
Published: (2025)
ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)
by: Coward, Samuel, et al.
Published: (2024)
AssertFix: Empowering Automated Assertion Fix via Large Language Models
by: Lyu, Hongqin, et al.
Published: (2025)
by: Lyu, Hongqin, et al.
Published: (2025)
Similar Items
-
UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024) -
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
by: Wang, Ning, et al.
Published: (2025) -
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025) -
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026) -
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
by: Wang, Ning, et al.
Published: (2024)