ADOR: A Design Exploration Framework for LLM Serving with Enhanced Latency and Throughput
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866910861459718144 |
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| author | Kim, Junsoo Lee, Hunjong Ko, Geonwoo Choi, Gyubin Ham, Seri Hong, Seongmin Kim, Joo-Young |
| author_facet | Kim, Junsoo Lee, Hunjong Ko, Geonwoo Choi, Gyubin Ham, Seri Hong, Seongmin Kim, Joo-Young |
| contents | The growing adoption of Large Language Models (LLMs) across various domains has driven the demand for efficient and scalable AI-serving solutions. Deploying LLMs requires optimizations to manage their significant computational and data demands. The prefill stage processes large numbers of input tokens in parallel, increasing computational load, while the decoding stage relies heavily on memory bandwidth due to the auto-regressive nature of LLMs. Current hardware, such as GPUs, often fails to balance these demands, leading to inefficient utilization. While batching improves hardware efficiency, it delays response times, degrading Quality-of-Service (QoS). This disconnect between vendors, who aim to maximize resource efficiency, and users, who prioritize low latency, highlights the need for a better solution. To address this, we propose ADOR, a framework that automatically identifies and recommends hardware architectures tailored to LLM serving. By leveraging predefined architecture templates specialized for heterogeneous dataflows, ADOR optimally balances throughput and latency. It efficiently explores design spaces to suggest architectures that meet the requirements of both vendors and users. ADOR demonstrates substantial performance improvements, achieving 2.51x higher QoS and 4.01x better area efficiency compared to the A100 at high batch sizes, making it a robust solution for scalable and cost-effective LLM serving. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_04253 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ADOR: A Design Exploration Framework for LLM Serving with Enhanced Latency and Throughput Kim, Junsoo Lee, Hunjong Ko, Geonwoo Choi, Gyubin Ham, Seri Hong, Seongmin Kim, Joo-Young Hardware Architecture The growing adoption of Large Language Models (LLMs) across various domains has driven the demand for efficient and scalable AI-serving solutions. Deploying LLMs requires optimizations to manage their significant computational and data demands. The prefill stage processes large numbers of input tokens in parallel, increasing computational load, while the decoding stage relies heavily on memory bandwidth due to the auto-regressive nature of LLMs. Current hardware, such as GPUs, often fails to balance these demands, leading to inefficient utilization. While batching improves hardware efficiency, it delays response times, degrading Quality-of-Service (QoS). This disconnect between vendors, who aim to maximize resource efficiency, and users, who prioritize low latency, highlights the need for a better solution. To address this, we propose ADOR, a framework that automatically identifies and recommends hardware architectures tailored to LLM serving. By leveraging predefined architecture templates specialized for heterogeneous dataflows, ADOR optimally balances throughput and latency. It efficiently explores design spaces to suggest architectures that meet the requirements of both vendors and users. ADOR demonstrates substantial performance improvements, achieving 2.51x higher QoS and 4.01x better area efficiency compared to the A100 at high batch sizes, making it a robust solution for scalable and cost-effective LLM serving. |
| title | ADOR: A Design Exploration Framework for LLM Serving with Enhanced Latency and Throughput |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.04253 |