The Case for Persistent CXL switches
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866913733466390528 |
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| author | Hadi, Khan Shaikhul Mustafa, Naveed Ul Heinrich, Mark Solihin, Yan |
| author_facet | Hadi, Khan Shaikhul Mustafa, Naveed Ul Heinrich, Mark Solihin, Yan |
| contents | Compute Express Link (CXL) switch allows memory extension via PCIe physical layer to address increasing demand for larger memory capacities in data centers. However, CXL attached memory introduces 170ns to 400ns memory latency. This becomes a significant performance bottleneck for applications that host data in persistent memory as all updates, after traversing the CXL switch, must reach persistent domain to ensure crash consistent updates. We make a case for persistent CXL switch to persist updates as soon as they reach the switch and hence significantly reduce latency of persisting data. To enable this, we presented a system independent persistent buffer (PB) design that ensures data persistency at CXL switch. Our PB design provides 12\% speedup, on average, over volatile CXL switch. Our \textit{read forwarding} optimization improves speedup to 15\%. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_04991 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | The Case for Persistent CXL switches Hadi, Khan Shaikhul Mustafa, Naveed Ul Heinrich, Mark Solihin, Yan Hardware Architecture Compute Express Link (CXL) switch allows memory extension via PCIe physical layer to address increasing demand for larger memory capacities in data centers. However, CXL attached memory introduces 170ns to 400ns memory latency. This becomes a significant performance bottleneck for applications that host data in persistent memory as all updates, after traversing the CXL switch, must reach persistent domain to ensure crash consistent updates. We make a case for persistent CXL switch to persist updates as soon as they reach the switch and hence significantly reduce latency of persisting data. To enable this, we presented a system independent persistent buffer (PB) design that ensures data persistency at CXL switch. Our PB design provides 12\% speedup, on average, over volatile CXL switch. Our \textit{read forwarding} optimization improves speedup to 15\%. |
| title | The Case for Persistent CXL switches |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.04991 |