TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator
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arXiv
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| Format: | Preprint |
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2025
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| author | Vungarala, Deepak Elbtity, Mohammed E. Syed, Sumiya Alam, Sakila Pandit, Kartik Ghosh, Arnob Zand, Ramtin Angizi, Shaahin |
| author_facet | Vungarala, Deepak Elbtity, Mohammed E. Syed, Sumiya Alam, Sakila Pandit, Kartik Ghosh, Arnob Zand, Ramtin Angizi, Shaahin |
| contents | The increasing complexity and scale of Deep Neural Networks (DNNs) necessitate specialized tensor accelerators, such as Tensor Processing Units (TPUs), to meet various computational and energy efficiency requirements. Nevertheless, designing optimal TPU remains challenging due to the high domain expertise level, considerable manual design time, and lack of high-quality, domain-specific datasets. This paper introduces TPU-Gen, the first Large Language Model (LLM) based framework designed to automate the exact and approximate TPU generation process, focusing on systolic array architectures. TPU-Gen is supported with a meticulously curated, comprehensive, and open-source dataset that covers a wide range of spatial array designs and approximate multiply-and-accumulate units, enabling design reuse, adaptation, and customization for different DNN workloads. The proposed framework leverages Retrieval-Augmented Generation (RAG) as an effective solution for a data-scare hardware domain in building LLMs, addressing the most intriguing issue, hallucinations. TPU-Gen transforms high-level architectural specifications into optimized low-level implementations through an effective hardware generation pipeline. Our extensive experimental evaluations demonstrate superior performance, power, and area efficiency, with an average reduction in area and power of 92\% and 96\% from the manual optimization reference values. These results set new standards for driving advancements in next-generation design automation tools powered by LLMs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_05951 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator Vungarala, Deepak Elbtity, Mohammed E. Syed, Sumiya Alam, Sakila Pandit, Kartik Ghosh, Arnob Zand, Ramtin Angizi, Shaahin Hardware Architecture Artificial Intelligence The increasing complexity and scale of Deep Neural Networks (DNNs) necessitate specialized tensor accelerators, such as Tensor Processing Units (TPUs), to meet various computational and energy efficiency requirements. Nevertheless, designing optimal TPU remains challenging due to the high domain expertise level, considerable manual design time, and lack of high-quality, domain-specific datasets. This paper introduces TPU-Gen, the first Large Language Model (LLM) based framework designed to automate the exact and approximate TPU generation process, focusing on systolic array architectures. TPU-Gen is supported with a meticulously curated, comprehensive, and open-source dataset that covers a wide range of spatial array designs and approximate multiply-and-accumulate units, enabling design reuse, adaptation, and customization for different DNN workloads. The proposed framework leverages Retrieval-Augmented Generation (RAG) as an effective solution for a data-scare hardware domain in building LLMs, addressing the most intriguing issue, hallucinations. TPU-Gen transforms high-level architectural specifications into optimized low-level implementations through an effective hardware generation pipeline. Our extensive experimental evaluations demonstrate superior performance, power, and area efficiency, with an average reduction in area and power of 92\% and 96\% from the manual optimization reference values. These results set new standards for driving advancements in next-generation design automation tools powered by LLMs. |
| title | TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2503.05951 |