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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| Schlagworte: | |
| Online-Zugang: | https://arxiv.org/abs/2503.06057 |
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| _version_ | 1866913848440651776 |
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| author | Tharakan, Alin Thomas Philip, Prince T., Gokulan Kumar, Sumit Banerjee, Gaurab |
| author_facet | Tharakan, Alin Thomas Philip, Prince T., Gokulan Kumar, Sumit Banerjee, Gaurab |
| contents | This paper presents a low power, low cost transceiver architecture to implement radar-on-a-chip. The transceiver comprises of a full ultra-wideband (UWB) transmitter and a full UWB band receiver. A design methodology to maximize the tuning range of the voltage-controlled oscillator (VCO) is presented. At the transmitter side, a sub-harmonic mixer is used for signal up-conversion. The receiver low noise amplifier (LNA) has a 2 to 6 GHz input matching bandwidth with a power gain of 9 dB and a noise figure of 2.5 dB. The transceiver is implemented in Cadence EDA tools using 65nm CMOS technology. The system achieves a total dc power consumption of 50 mW. Good noise figure performance; good wide-band matching; gain; high level of integration; low power; low cost of the proposed UWB radar transceiver front-end make it a highly competitive SoC solution for low power UWB transceivers. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_06057 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A 2-6 GHz Ultra-Wideband CMOS Transceiver for Radar Applications Tharakan, Alin Thomas Philip, Prince T., Gokulan Kumar, Sumit Banerjee, Gaurab Systems and Control This paper presents a low power, low cost transceiver architecture to implement radar-on-a-chip. The transceiver comprises of a full ultra-wideband (UWB) transmitter and a full UWB band receiver. A design methodology to maximize the tuning range of the voltage-controlled oscillator (VCO) is presented. At the transmitter side, a sub-harmonic mixer is used for signal up-conversion. The receiver low noise amplifier (LNA) has a 2 to 6 GHz input matching bandwidth with a power gain of 9 dB and a noise figure of 2.5 dB. The transceiver is implemented in Cadence EDA tools using 65nm CMOS technology. The system achieves a total dc power consumption of 50 mW. Good noise figure performance; good wide-band matching; gain; high level of integration; low power; low cost of the proposed UWB radar transceiver front-end make it a highly competitive SoC solution for low power UWB transceivers. |
| title | A 2-6 GHz Ultra-Wideband CMOS Transceiver for Radar Applications |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2503.06057 |