Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs

Fuente: arXiv

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Bibliographic Details
Main Authors:	Wu, Qizhe, Liang, Huawen, Gui, Yuchen, Zeng, Zhichen, He, Zerong, Tao, Linfeng, Wang, Xiaotian, Zhao, Letian, Zeng, Zhaoxi, Yuan, Wei, Wu, Wei, Jin, Xi
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Machine Learning
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2503.06342