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Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs

Fuente: arXiv

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Dettagli Bibliografici
Autori principali:	Wu, Qizhe, Liang, Huawen, Gui, Yuchen, Zeng, Zhichen, He, Zerong, Tao, Linfeng, Wang, Xiaotian, Zhao, Letian, Zeng, Zhaoxi, Yuan, Wei, Wu, Wei, Jin, Xi
Natura:	Preprint
Pubblicazione:	2025
Soggetti:	Hardware Architecture Machine Learning
Accesso online:	Acceder al recurso
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