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| Autori principali: | , , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| Soggetti: | |
| Accesso online: | https://arxiv.org/abs/2503.06448 |
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| _version_ | 1866912265811263488 |
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| author | Cheng, Xiaoyu Hu, Yangyang Miao, Tianci Liu, Wenbo Zheng, Qihang Liu, Yisi Liang, Jie Chen, Liang Guo, Aiying Yin, Luqiao Zhang, Jianhua Ren, Kailin |
| author_facet | Cheng, Xiaoyu Hu, Yangyang Miao, Tianci Liu, Wenbo Zheng, Qihang Liu, Yisi Liang, Jie Chen, Liang Guo, Aiying Yin, Luqiao Zhang, Jianhua Ren, Kailin |
| contents | The complementary field-effect transistors (CFETs), featuring vertically stacked n/p-FETs, enhance integration density and significantly reduce the area of standard cells such as static random-access memory (SRAM). However, the advantage of area scaling through CFETs is hindered by the imbalance in N/P transistor counts (typically 4N/2P) within SRAM cells. In this work, we propose a novel 6T-SRAM design using three sets of CFETs, achieved by vertically stacking two n-FET pass-gate (PG) transistors via the CFET architecture. Through TCAD simulations, we optimize channel doping concentration and the number of top/bottom nanosheets (NS), demonstrating that junctionless accumulation mode (JAM) devices outperform inversion mode (IM) devices for PG and pull-down (PD) transistors. The proposed design achieves a 37% area reduction in SRAM standard cell layout compared to conventional CFET-based SRAM. With optimized parameters (n-type doping of \(1\times10^{15}\) cm\(^{-3}\) and '1B4T' NS configuration), the 3-CFET SRAM exhibits superior write margin (349.60 mV) and write delay (54.4 ps). This work advances SRAM design within the CFET framework, offering a scalable solution for next-generation memory technologies. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_06448 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Novel Design for SRAM Bitcell with 3-Complementary-FETs Cheng, Xiaoyu Hu, Yangyang Miao, Tianci Liu, Wenbo Zheng, Qihang Liu, Yisi Liang, Jie Chen, Liang Guo, Aiying Yin, Luqiao Zhang, Jianhua Ren, Kailin Applied Physics The complementary field-effect transistors (CFETs), featuring vertically stacked n/p-FETs, enhance integration density and significantly reduce the area of standard cells such as static random-access memory (SRAM). However, the advantage of area scaling through CFETs is hindered by the imbalance in N/P transistor counts (typically 4N/2P) within SRAM cells. In this work, we propose a novel 6T-SRAM design using three sets of CFETs, achieved by vertically stacking two n-FET pass-gate (PG) transistors via the CFET architecture. Through TCAD simulations, we optimize channel doping concentration and the number of top/bottom nanosheets (NS), demonstrating that junctionless accumulation mode (JAM) devices outperform inversion mode (IM) devices for PG and pull-down (PD) transistors. The proposed design achieves a 37% area reduction in SRAM standard cell layout compared to conventional CFET-based SRAM. With optimized parameters (n-type doping of \(1\times10^{15}\) cm\(^{-3}\) and '1B4T' NS configuration), the 3-CFET SRAM exhibits superior write margin (349.60 mV) and write delay (54.4 ps). This work advances SRAM design within the CFET framework, offering a scalable solution for next-generation memory technologies. |
| title | A Novel Design for SRAM Bitcell with 3-Complementary-FETs |
| topic | Applied Physics |
| url | https://arxiv.org/abs/2503.06448 |