Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

Fuente: arXiv
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Bibliographic Details
Main Authors: Nakano, Hiroshi, Blachut, Krzysztof, Jeziorek, Kamil, Wzorek, Piotr, Dampfhoffer, Manon, Mesquida, Thomas, Nishi, Hiroaki, Kryjak, Tomasz, Dalgaty, Thomas
Format: Preprint
Published: 2025
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