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Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

Fuente: arXiv

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Détails bibliographiques
Auteurs principaux:	Nakano, Hiroshi, Blachut, Krzysztof, Jeziorek, Kamil, Wzorek, Piotr, Dampfhoffer, Manon, Mesquida, Thomas, Nishi, Hiroaki, Kryjak, Tomasz, Dalgaty, Thomas
Format:	Preprint
Publié:	2025
Sujets:	Machine Learning Artificial Intelligence Signal Processing
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

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