Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866913732990337024 |
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| author | Short, Benedict McInerney, Ian Wickerson, John |
| author_facet | Short, Benedict McInerney, Ian Wickerson, John |
| contents | Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_09463 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress) Short, Benedict McInerney, Ian Wickerson, John Software Engineering Hardware Architecture Programming Languages Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog. |
| title | Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress) |
| topic | Software Engineering Hardware Architecture Programming Languages |
| url | https://arxiv.org/abs/2503.09463 |