A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology
Fuente:
arXiv
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| Autori principali: | , , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866913737734094848 |
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| author | Kim, Daewung Jeon, Seong Hwan Jeon, Young Hee Kwon, Kyung-Bae Kim, Jigon Choi, Yeounghun Cha, Hyunseung Kwon, Kitae Park, Daesik Lee, Jongseuk Kim, Sihwan Song, Seung-Hwan |
| author_facet | Kim, Daewung Jeon, Seong Hwan Jeon, Young Hee Kwon, Kyung-Bae Kim, Jigon Choi, Yeounghun Cha, Hyunseung Kwon, Kitae Park, Daesik Lee, Jongseuk Kim, Sihwan Song, Seung-Hwan |
| contents | This study introduces a novel AI microcontroller optimized for cost-effective, battery-powered edge AI applications. Unlike traditional single bit/cell memory configurations, the proposed microcontroller integrates zero-standby power weight memory featuring standard logic compatible 4-bits/cell embedded flash technology tightly coupled to a Near-Memory Computing Unit. This architecture enables efficient and low-power AI acceleration. Advanced state mapping and an overstress-free word line (WL) driver circuit extend verify levels, ensuring robust 16 state cell margin. A ping-pong buffer reduces internal data movement while supporting simultaneous multi-bit processing. The fabricated microcontroller demonstrated high reliability, maintaining accuracy after 160 hours of unpowered baking at 125$^\circ$C. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_11660 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology Kim, Daewung Jeon, Seong Hwan Jeon, Young Hee Kwon, Kyung-Bae Kim, Jigon Choi, Yeounghun Cha, Hyunseung Kwon, Kitae Park, Daesik Lee, Jongseuk Kim, Sihwan Song, Seung-Hwan Hardware Architecture Artificial Intelligence This study introduces a novel AI microcontroller optimized for cost-effective, battery-powered edge AI applications. Unlike traditional single bit/cell memory configurations, the proposed microcontroller integrates zero-standby power weight memory featuring standard logic compatible 4-bits/cell embedded flash technology tightly coupled to a Near-Memory Computing Unit. This architecture enables efficient and low-power AI acceleration. Advanced state mapping and an overstress-free word line (WL) driver circuit extend verify levels, ensuring robust 16 state cell margin. A ping-pong buffer reduces internal data movement while supporting simultaneous multi-bit processing. The fabricated microcontroller demonstrated high reliability, maintaining accuracy after 160 hours of unpowered baking at 125$^\circ$C. |
| title | A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2503.11660 |