A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866916727880679424 |
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| author | Jiang, Xun Lu, Haoran Zhao, Yuxuan Wang, Jiarui Guo, Zizheng Wu, Heng Yu, Bei Lim, Sung Kyu Wang, Runsheng Huang, Ru Lin, Yibo |
| author_facet | Jiang, Xun Lu, Haoran Zhao, Yuxuan Wang, Jiarui Guo, Zizheng Wu, Heng Yu, Bei Lim, Sung Kyu Wang, Runsheng Huang, Ru Lin, Yibo |
| contents | As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest, several works have hacked existing backend tools to explore the potential of synthesizing double-side clock trees via nano Through-Silicon-Vias (nTSVs). However, these works lack a systematic perspective on design resource allocation and multi-objective optimization. We propose a systematic approach to design clock trees with double-side metal layers, including hierarchical clock routing, concurrent buffers and nTSVs insertion, and skew refinement. Compared with the state-of-the-art (SOTA) methods, the widely-used open-source tool, our algorithm outperforms them in latency, skew, wirelength, and the number of buffers and nTSVs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_12512 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis Jiang, Xun Lu, Haoran Zhao, Yuxuan Wang, Jiarui Guo, Zizheng Wu, Heng Yu, Bei Lim, Sung Kyu Wang, Runsheng Huang, Ru Lin, Yibo Hardware Architecture As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest, several works have hacked existing backend tools to explore the potential of synthesizing double-side clock trees via nano Through-Silicon-Vias (nTSVs). However, these works lack a systematic perspective on design resource allocation and multi-objective optimization. We propose a systematic approach to design clock trees with double-side metal layers, including hierarchical clock routing, concurrent buffers and nTSVs insertion, and skew refinement. Compared with the state-of-the-art (SOTA) methods, the widely-used open-source tool, our algorithm outperforms them in latency, skew, wirelength, and the number of buffers and nTSVs. |
| title | A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.12512 |