VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Fuente:
arXiv
Saved in:
| Main Authors: | Wang, Zeng, Shao, Minghao, Nabeel, Mohammed, Roy, Prithwish Basu, Mankali, Likhitha, Bhandari, Jitendra, Karri, Ramesh, Sinanoglu, Ozgur, Shafique, Muhammad, Knechtel, Johann |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
by: Roy, Prithwish Basu, et al.
Published: (2026)
by: Roy, Prithwish Basu, et al.
Published: (2026)
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)
by: Roy, Prithwish Basu, et al.
Published: (2025)
Lightweight Countermeasures Against Static Power Side-Channel Attacks
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)
by: Wang, Zeng, et al.
Published: (2024)
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)
by: Knechtel, Johann, et al.
Published: (2026)
Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)
by: Karn, Rupesh Raj, et al.
Published: (2025)
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)
by: Fu, Weimin, et al.
Published: (2026)
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
by: Shao, Minghao, et al.
Published: (2026)
by: Shao, Minghao, et al.
Published: (2026)
SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
by: Fu, Weimin, et al.
Published: (2026)
by: Fu, Weimin, et al.
Published: (2026)
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)
by: Sreekumar, Saideep, et al.
Published: (2026)
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
by: Collini, Luca, et al.
Published: (2026)
by: Collini, Luca, et al.
Published: (2026)
Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)
by: Mashburn, Joshua, et al.
Published: (2025)
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
by: Saha, Akashdeep, et al.
Published: (2025)
by: Saha, Akashdeep, et al.
Published: (2025)
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
by: Wang, Zeng, et al.
Published: (2026)
by: Wang, Zeng, et al.
Published: (2026)
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
Large Language Models (LLMs) for Electronic Design Automation (EDA)
by: Xu, Kangwei, et al.
Published: (2025)
by: Xu, Kangwei, et al.
Published: (2025)
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
by: Blocklove, Jason, et al.
Published: (2024)
by: Blocklove, Jason, et al.
Published: (2024)
LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs
by: Perera, Buddhi, et al.
Published: (2026)
by: Perera, Buddhi, et al.
Published: (2026)
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
by: Jin, Pengwei, et al.
Published: (2025)
by: Jin, Pengwei, et al.
Published: (2025)
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)
by: Wang, Fangzhou, et al.
Published: (2024)
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
by: Tan, Yan, et al.
Published: (2025)
by: Tan, Yan, et al.
Published: (2025)
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
by: Tan, Yan, et al.
Published: (2026)
by: Tan, Yan, et al.
Published: (2026)
VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
by: Thorat, Kiran, et al.
Published: (2025)
by: Thorat, Kiran, et al.
Published: (2025)
TrojanLoC: LLM-based Framework for RTL Trojan Localization
by: Xiao, Weihua, et al.
Published: (2025)
by: Xiao, Weihua, et al.
Published: (2025)
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
by: Zhao, Jiayu, et al.
Published: (2025)
by: Zhao, Jiayu, et al.
Published: (2025)
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)
by: Wang, Ning, et al.
Published: (2025)
EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025)
by: Guo, Ping, et al.
Published: (2025)
VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
by: Wang, Yiting, et al.
Published: (2025)
by: Wang, Yiting, et al.
Published: (2025)
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
Similar Items
-
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025) -
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024) -
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
by: Roy, Prithwish Basu, et al.
Published: (2026) -
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025) -
Lightweight Countermeasures Against Static Power Side-Channel Attacks
by: Bhandari, Jitendra, et al.
Published: (2024)