OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
Fuente:
arXiv
Guardado en:
| Autores principales: | Liu, Shang, Lu, Yao, Fang, Wenji, Li, Mengming, Xie, Zhiyao |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
por: Liu, Shang, et al.
Publicado: (2023)
por: Liu, Shang, et al.
Publicado: (2023)
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
por: Li, Mengming, et al.
Publicado: (2024)
por: Li, Mengming, et al.
Publicado: (2024)
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
por: Fang, Wenji, et al.
Publicado: (2024)
por: Fang, Wenji, et al.
Publicado: (2024)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
por: Fang, Wenji, et al.
Publicado: (2026)
por: Fang, Wenji, et al.
Publicado: (2026)
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
por: Yan, Zhiyuan, et al.
Publicado: (2024)
por: Yan, Zhiyuan, et al.
Publicado: (2024)
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
por: Fang, Wenji, et al.
Publicado: (2024)
por: Fang, Wenji, et al.
Publicado: (2024)
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
por: Fang, Wenji, et al.
Publicado: (2025)
por: Fang, Wenji, et al.
Publicado: (2025)
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
por: Zhang, Qijun, et al.
Publicado: (2025)
por: Zhang, Qijun, et al.
Publicado: (2025)
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
por: Wu, Yuchao, et al.
Publicado: (2026)
por: Wu, Yuchao, et al.
Publicado: (2026)
RTL++: Graph-enhanced LLM for RTL Code Generation
por: Akyash, Mohammad, et al.
Publicado: (2025)
por: Akyash, Mohammad, et al.
Publicado: (2025)
Profile-Guided Temporal Prefetching
por: Li, Mengming, et al.
Publicado: (2025)
por: Li, Mengming, et al.
Publicado: (2025)
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
por: Zhang, Qijun, et al.
Publicado: (2025)
por: Zhang, Qijun, et al.
Publicado: (2025)
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
por: Fang, Wenji, et al.
Publicado: (2025)
por: Fang, Wenji, et al.
Publicado: (2025)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
por: Yin, Shuo, et al.
Publicado: (2026)
por: Yin, Shuo, et al.
Publicado: (2026)
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
por: Zhang, Qijun, et al.
Publicado: (2025)
por: Zhang, Qijun, et al.
Publicado: (2025)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
por: Allam, Ahmed, et al.
Publicado: (2024)
por: Allam, Ahmed, et al.
Publicado: (2024)
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
por: Maddala, Karthik, et al.
Publicado: (2024)
por: Maddala, Karthik, et al.
Publicado: (2024)
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
por: Fang, Wenji, et al.
Publicado: (2025)
por: Fang, Wenji, et al.
Publicado: (2025)
Understanding and Mitigating Errors of LLM-Generated RTL Code
por: Zhang, Jiazheng, et al.
Publicado: (2025)
por: Zhang, Jiazheng, et al.
Publicado: (2025)
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
por: Zhang, Qijun, et al.
Publicado: (2024)
por: Zhang, Qijun, et al.
Publicado: (2024)
FormalRTL: Verified RTL Synthesis at Scale
por: Li, Kezhi, et al.
Publicado: (2026)
por: Li, Kezhi, et al.
Publicado: (2026)
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
por: Purini, Suresh, et al.
Publicado: (2025)
por: Purini, Suresh, et al.
Publicado: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
por: Chen, Lu, et al.
Publicado: (2025)
por: Chen, Lu, et al.
Publicado: (2025)
ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
por: Sheth, Arnav, et al.
Publicado: (2025)
por: Sheth, Arnav, et al.
Publicado: (2025)
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
por: Ye, Junhao, et al.
Publicado: (2026)
por: Ye, Junhao, et al.
Publicado: (2026)
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
por: Yu, Zhongzhi, et al.
Publicado: (2025)
por: Yu, Zhongzhi, et al.
Publicado: (2025)
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
por: Li, Mengming, et al.
Publicado: (2025)
por: Li, Mengming, et al.
Publicado: (2025)
From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
por: Wang, Yonghao, et al.
Publicado: (2026)
por: Wang, Yonghao, et al.
Publicado: (2026)
Assessing Large Language Models in Generating RTL Design Specifications
por: Huang, Hung-Ming, et al.
Publicado: (2025)
por: Huang, Hung-Ming, et al.
Publicado: (2025)
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
por: Fang, Wenji, et al.
Publicado: (2025)
por: Fang, Wenji, et al.
Publicado: (2025)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
por: Deng, Chenhui, et al.
Publicado: (2026)
por: Deng, Chenhui, et al.
Publicado: (2026)
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
por: Ye, Junhao, et al.
Publicado: (2025)
por: Ye, Junhao, et al.
Publicado: (2025)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
por: Deng, Chenhui, et al.
Publicado: (2025)
por: Deng, Chenhui, et al.
Publicado: (2025)
Extend IVerilog to Support Batch RTL Fault Simulation
por: Tang, Jiaping, et al.
Publicado: (2025)
por: Tang, Jiaping, et al.
Publicado: (2025)
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
por: Li, Wenkai, et al.
Publicado: (2025)
por: Li, Wenkai, et al.
Publicado: (2025)
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
por: Shi, Zhengyuan, et al.
Publicado: (2026)
por: Shi, Zhengyuan, et al.
Publicado: (2026)
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
por: Calzada, Paul E., et al.
Publicado: (2025)
por: Calzada, Paul E., et al.
Publicado: (2025)
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
por: Pinckney, Nathaniel, et al.
Publicado: (2025)
por: Pinckney, Nathaniel, et al.
Publicado: (2025)
IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
por: Chen, Luanrong, et al.
Publicado: (2026)
por: Chen, Luanrong, et al.
Publicado: (2026)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
por: Krupp, Lukas, et al.
Publicado: (2026)
por: Krupp, Lukas, et al.
Publicado: (2026)
Ejemplares similares
-
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
por: Liu, Shang, et al.
Publicado: (2023) -
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
por: Li, Mengming, et al.
Publicado: (2024) -
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
por: Fang, Wenji, et al.
Publicado: (2024) -
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
por: Fang, Wenji, et al.
Publicado: (2026) -
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
por: Yan, Zhiyuan, et al.
Publicado: (2024)