Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation
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arXiv
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| Autori principali: | , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866910896091037696 |
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| author | Pradhan, Ashutosh Ottaviano, Daniele Jiang, Yi Huang, Haozheng Zuepke, Alexander Bastoni, Andrea Caccamo, Marco |
| author_facet | Pradhan, Ashutosh Ottaviano, Daniele Jiang, Yi Huang, Haozheng Zuepke, Alexander Bastoni, Andrea Caccamo, Marco |
| contents | The increasing complexity of embedded hardware platforms poses significant challenges for real-time workloads. Architectural features such as Intel RDT, Arm QoS, and Arm MPAM are either unavailable on commercial embedded platforms or designed primarily for server environments optimized for average-case performance and might fail to deliver the expected real-time guarantees. Arm DynamIQ Shared Unit (DSU) includes isolation features-among others, hardware per-way cache partitioning-that can improve the real-time guarantees of complex embedded multicore systems and facilitate real-time analysis. However, the DSU also targets average cases, and its real-time capabilities have not yet been evaluated. This paper presents the first comprehensive analysis of three real-world deployments of the Arm DSU on Rockchip RK3568, Rockchip RK3588, and NVIDIA Orin platforms. We integrate support for the DSU at the operating system and hypervisor level and conduct a large-scale evaluation using both synthetic and real-world benchmarks with varying types and intensities of interference. Our results make extensive use of performance counters and indicate that, although effective, the quality of partitioning and isolation provided by the DSU depends on the type and the intensity of the interfering workloads. In addition, we uncover and analyze in detail the correlation between benchmarks and different types and intensities of interference. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_17038 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation Pradhan, Ashutosh Ottaviano, Daniele Jiang, Yi Huang, Haozheng Zuepke, Alexander Bastoni, Andrea Caccamo, Marco Performance Hardware Architecture 68M20 C.3; C.4; D.4.7 The increasing complexity of embedded hardware platforms poses significant challenges for real-time workloads. Architectural features such as Intel RDT, Arm QoS, and Arm MPAM are either unavailable on commercial embedded platforms or designed primarily for server environments optimized for average-case performance and might fail to deliver the expected real-time guarantees. Arm DynamIQ Shared Unit (DSU) includes isolation features-among others, hardware per-way cache partitioning-that can improve the real-time guarantees of complex embedded multicore systems and facilitate real-time analysis. However, the DSU also targets average cases, and its real-time capabilities have not yet been evaluated. This paper presents the first comprehensive analysis of three real-world deployments of the Arm DSU on Rockchip RK3568, Rockchip RK3588, and NVIDIA Orin platforms. We integrate support for the DSU at the operating system and hypervisor level and conduct a large-scale evaluation using both synthetic and real-world benchmarks with varying types and intensities of interference. Our results make extensive use of performance counters and indicate that, although effective, the quality of partitioning and isolation provided by the DSU depends on the type and the intensity of the interfering workloads. In addition, we uncover and analyze in detail the correlation between benchmarks and different types and intensities of interference. |
| title | Arm DynamIQ Shared Unit and Real-Time: An Empirical Evaluation |
| topic | Performance Hardware Architecture 68M20 C.3; C.4; D.4.7 |
| url | https://arxiv.org/abs/2503.17038 |